Combination field programmable gate array allowing dynamic reprogrammability
AssigneeKLP International, Ltd.
InventorsJack Zezhong Peng, Zhongshang Liu, David Fong, Fei Ye
Life of this patent
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Abstract
A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.
Claims18
A dynamic memory cell for storing data used in programming a field programmable gate array (FPGA), the cell useful in an array having column write bitlines, read bitlines, and row wordlines, the cell comprising:
- a select transistor having a gate, a source, and a drain, said gate connected to a write bitline, said source connected to a floating point node, and said drain connected to a row wordline;
- a sense device for determining the data on said floating point node, said sense device connected between said read bitline and said row wordline;
- and
- a switch being controlled by said floating point node, wherein said floating point control node stores data as a voltage indicative of a one or a zero.
A dynamic memory cell for storing data, the cell useful in an array having column write bitlines, read bitlines, and row wordlines, the cell comprising:
- a select transistor having a gate, a source, and a drain, said gate connected to a write bitline, said source connected to a floating point node, and said drain connected to a row wordline;
- and
- a sense device for determining the data on said floating point node, said sense device comprising a transistor arrangement connected between said read bitline and said row wordline, said transistor arrangement having a control gate connected to said floating point node.
A dynamic memory cell for storing data, the cell useful in an array having column write bitlines, read bitlines, and row wordlines, the cell comprising:
- a select transistor having a gate, a source, and a drain, said gate connected to a write bitline, said source connected to a floating point node, and said drain connected to a row wordline;
- and
- a switch being controlled by said floating point node, wherein said floating point control node stores data as a voltage indicative of a one or a zero.
A dynamic memory cell for storing data used in programming a field programmable gate array (FPGA), the cell having column write bitlines, read bitlines, and row wordlines, the cell comprising:
- a select transistor having a gate, a source, and a drain, said gate connected to a write bitline, said source connected to a floating point node, and said drain connected to a row wordline;
- and
- a switch being controlled by said floating point node, wherein said floating point control node stores data as a voltage indicative of a one or a zero, wherein during programming of said switch, said floating point node has a voltage higher than the source or drain of said switch.
Dependencies are inferred from the claim text.