Ferroelectric memory device and read control method thereof

A ferroelectric memory device comprising:

• a memory cell array including a matrix layout of memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a plate line and a remaining end connected via said transistor to a bit line;
• a plate-line drive circuit for driving said plate line;
• a word-line drive circuit for driving said word line;
• a sense amplifier connected to said bit line for detecting and amplifying data of said memory cell;
• and
• at least one of said plate-line drive circuit and said word-line drive circuit having a pullup PMOS transistor for potentially raising an output terminal from a low level up to a high level, a pulldown NMOS transistor for causing said output terminal to potentially drop from the high level down to the low level, and a delay element responsive to receipt of a timing signal for complementarily driving gates of said pullup PMOS transistor and said pulldown NMOS transistor while simultaneously letting these transistors vary in drivability.

A read control method of a ferroelectric memory device including a cell block formed of a series connection of plural memory cells each having a transistor with its gate connected to a word line and a ferroelectric capacitor having one end connected to a bit line and a remaining end connected to a plate line, each said memory cell being such that both ends of said ferroelectric capacitor are connected to a source and a drain of said transistor, and said cell block having one end connected to said bit line through a block select transistor and a remaining end connected to said plate line, said method comprising:

• a first step of causing each transistor of said plural memory cells to turn on resulting in these memory cells being set in a non-select state while letting said cell block be electrically disconnected from said bit line;
• a second step of driving, after said first step, said word line so that the transistor of a memory cell to be subjected to data readout in said plural memory cells turns off to thereby select this memory cell while simultaneously setting said bit line in an electrically floating state:
• a third step of reading, after said second step, a signal voltage out of the selected memory cell onto said bit line by driving said plate line and also by turning said block select transistor on to thereby connect said cell block to said bit line;
• and
• said third step including causing said plate line to vary in drivability during its driving.