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US 7,064,971 B2Granted
Methods for saving power and area for content addressable memory devices
OwnerJeng-Jye Shauinventor
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Abstract
Using 6 transistor memory cell to replace prior art 10 transistor binary content addressable memory (CAM) cells, and using 10 transistor ternary CAM (TCAM) cell to replace prior art 16 transistor TCAM cells, the present invention provided significant cost saving for high density CAM products. The power consumption problems of prior art high density CAM devices are solved by novel zoned lookup mechanism. For a high density CAM storing sorted data, lookup mechanisms of the present invention can reduce power consumption by two orders of magnitudes.
Claims6
A content addressable memory (CAM) cell comprising:
- four transistors configured as a back-to-back inverter for forming a bi-stable memory having a first and a second memory nodes for storing a pair of stored complimentary binary bits;
- a fifth transistor connected to said first memory node and a conductive line connected to said second memory nodes for receiving a pair of input complimentary binary bits therefrom;
- and
- an exclusive OR logic circuit comprising four transistors connected to said back-to-back inverter for comparing said input complimentary binary bits with said pair of stored complimentary binary bits for generating a match-mismatch signal;
- and
- a gate of said fifth transistor further connected to a wordline driver for controlling different read and write relative wordline voltages for carrying out a single-bit-line-write (SBLW) operation for writing said pair of complimentary binary bits to said first and second memory nodes.
3 more elements
Dependencies are inferred from the claim text.