Serial transistor-cell array architecture
AssigneeMicron Technology, Inc.
InventorHagop A. Nazarian
Life of this patent
Estimating the term…
Abstract
A memory array architecture suitable for variable resistance memory that mitigates sneak path and associated problems by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is an even number of at least 2; there may or may not be an equal number of cells on either side of the transistor. The memory array has memory cells, which are grouped into 1T-2nCell blocks.
Claims25
An array architecture for a memory device, comprising a memory cell block comprising an even number of memory cells and a transistor, wherein said memory cells are electrically coupled to said transistor such that at least one of the memory cells is on a first side of said transistor and at least one other memory cell is on a second side of said transistor, said memory cells comprising variable resistance memory elements,
- wherein at least two memory cells are electrically coupled to each side of said transistor.
An array architecture for a memory device, comprising a memory cell block comprising an even number of memory cells and a transistor, wherein said memory cells are electrically coupled to said transistor such that at least one of the memory cells is on a first side of said transistor and at least one other memory cell is on a second side of said transistor, said memory cells comprising variable resistance memory elements,
- wherein each memory cell is in electrical communication with a respective bit line and upon addressing a first memory cell of said memory cell block a sneak path includes any second memory cell of said memory cell block that is electrically coupled to a same side of said transistor as said first memory cell and any third memory cell electrically coupled to a same bit line as said first and second memory cells.
An array architecture for a memory device, comprising a memory cell block comprising an even number of memory cells and a transistor, wherein said memory cells are electrically coupled to said transistor such that at least one of the memory cells is on a first side of said transistor and at least one other memory cell is on a second side of said transistor, said memory cells comprising variable resistance memory elements,
- wherein each memory cell is in electrical communication with a respective bit line, a gate of said transistor is electrically coupled to a wordline and a sneak path resistance is [R/(n−1)]+[R/(m(n−1))], where R is a combined resistance of each memory cell of said sneak path, n is a number of memory cells of said memory cell block electrically coupled to a same side of said transistor as an addressed memory cell, and m is a total number of wordlines of the array architecture.
A memory device comprising:
- at least two first memory cells;
- at least two second memory cells;
- and
- a gate electrode electrically coupling said first memory cells to said second memory cells, wherein at least one said first memory cell is addressed for reading through at least one said second memory cell and said gate electrode;
- wherein said memory cells comprise variable resistance memory elements.
A memory device comprising:
- at least a first memory cell;
- at least a second memory cell;
- a gate electrode electrically coupling said first memory cell to said second memory cell, wherein said first memory cell is addressed for reading through said second memory cell and said gate electrode;
- a first bit line in electrical communication with said first memory cell and a sensing circuit;
- a second bit line in electrical communication with said second memory cell;
- and
- a wordline in electrical communication with said gate electrode;
- wherein said first and second bit lines and said wordline are included in a read circuit which is generated upon grounding of said first bit line, forcing current on said second bit line, and applying voltage to said wordline, said read circuit having a sneak path resistance of [R/(n−1)]+[R/(m(n−1))], where R is a combined resistance of each said memory cell, n is a number of first memory cells, and m is a total number of wordlines of an array of the memory device.
A processor system, comprising:
- a processor;
- and
- a memory circuit, comprising a memory cell block having a plurality of memory cells and a transistor, wherein said memory cells are electrically coupled to said transistor such that at least one of the memory cells is on a first side of said transistor and at least one other memory cell is on a second side of said transistor;
- wherein said memory cells comprise variable resistance memory elements and at least two memory cells are electrically coupled to each side of said transistor.
A method of reading stored data, comprising:
- forming an electrical circuit between an addressed memory cell and a second memory cell, said circuit comprising a transistor gate electrically coupling said addressed memory cell to said second memory cell;
- sensing a resistance state of the addressed cell through the circuit;
- and
- calculating a sneak path resistance for said read circuit as [R/(n−1)]+[R/(m(n−1))], where R is a combined resistance of each memory cell of said read circuit, n is a number of memory cells electrically coupled to said transistor at a same side as said addressed memory cell, and m is a total number of wordlines,
- wherein said memory cells comprise variable resistance memory elements.
Dependencies are inferred from the claim text.