Differential switching circuit and digital-to-analog converter

A differential switching circuit comprising:

• a transistor pair including a first transistor whose first terminal is coupled to a common node and whose second terminal is coupled to a first output node, and a second transistor whose first terminal is coupled to the common node and whose second terminal is coupled to a second output node;
• a current source configured to supply a substantially uniform current signal to the common node;
• a first dynamic inverter configured to drive the first transistor in response to an input data signal and configured to cause the first transistor to operate in a saturation operation region regardless of a voltage variation of the first output node when the first transistor is turned on;
• and
• a second dynamic inverter configured to drive the second transistor in response to an inverted input data signal that is opposite in phase to the input data to cause the second transistor to operate in the saturation region regardless of a voltage variation of the second output node when the second transistor is turned on;
• wherein each of the first and second dynamic inverters comprises:
• a third transistor coupled between a first power voltage and a control electrode of the first transistor or a control electrode of the second transistor and configured to receive the input data signal or the inverted input data signal through a control electrode thereof;
• a fourth transistor coupled between a first node and the control electrode of the first transistor or the control electrode of the second transistor and configured to receive the input data signal or the inverted input data signal through a control electrode thereof;
• and
• a fifth transistor coupled between the first node and a second power voltage, the fifth transistor having a control electrode coupled to the control electrode of the first transistor or the control electrode of the second transistor.

A digital-to-analog converter comprising:

• an input part configured to receive and store a digital data signal;
• a decoder configured to decode the digital data signal from the input part to generate a switching driving data signal corresponding to the decoded digital data signal;
• a current cell array comprising a plurality of current cells, each current cell of the current cell array including a pair of transistors having a common source configuration which are selectively switched by the switching driving data signal to provide a unit current signal to an output terminal of a pair of output terminals, and the current cell array controlling the turned-on transistor of the transistor pair having the common source configuration to operate in a saturation region regardless of a voltage variation at the output terminal of the turned-on transistor when one transistor of the commonly coupled transistor pair is turned on, the pair of transistors including a first transistor coupled between one output terminal of the pair of output terminals and a common node and a second transistor coupled between an other output terminal of the pair of output terminals and the common node;
• and
• an output part configured to output an analog signal corresponding to the digital data signal based on a difference between a sum of unit current signals provided through one output terminal of each of the current cells of the current cell array and a sum of unit current signals provided through the other output terminal of each of the current cells of the current cell array, wherein each of the current cells further comprises:
• a current source configured to supply a substantially uniform current signal to the common node:
• a first driver configured to generate a first driving signal to apply the first driving signal to a control electrode of the first transistor so as to complementarily drive the first and second transistors in response to the switching driving data signal;
• and
• a second driver configured to generate a second driving signal in response to an inverted input signal from the switching driving data signal and configured to apply the second driving signal to a control electrode of the second transistor, and wherein each of the first and second drivers comprises:
• a third transistor coupled between a first power voltage and the control electrode of the first or second transistor and configured to receive the switching driving data signal or the inverted input data signal through a control electrode thereof;
• a fourth transistor coupled between a first node and the control electrode of the first or second transistor and configured to receive the switching driving data signal or the inverted input data signal through a control electrode thereof;
• and
• a fifth transistor coupled between the first node and a second power voltage, the fifth transistor having a control electrode coupled to the control electrode of the first or second transistor.