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US 7,064,694 B1Granted
Multi-cycle, multi-slope analog to digital converter
AssigneeTexas Instruments Incorporated
InventorsBarry Jon Male, Wilbur Madison Miller, Jr.
Life of this patent
Estimating the term…
Abstract
A multi-cycle, multi-slope analog to digital converter overlaps charge and discharge periods to reduce latency to the end of the measurement following a sampling window. Additionally, charging and discharging of an integration capacitor during the measurement cycle occurs between defined thresholds so as to avoid saturation within the analog to digital converter.
Claims40
A method of producing a digital representation of an analog input signal comprising the steps of:
- a. in response to a first control signal, producing a timing signal that defines a sampling window having a time interval timed by a clock having a plurality of clock cycles;
- b. responsive to the start of said sampling window enabling a first current source that produces a first current that is proportional to said analog input signal and performing a first integration function to produce a ramp voltage on an integration capacitor coupled to said first current source, wherein said ramp voltage has a starting voltage at the start of said sampling window and said ramp voltage generally has a first slope of a first direction during a first ramp voltage portion, wherein said first current source ceases to perform said first integration function at the end of said sampling window;
- c. at least in part in response to said first ramp voltage portion intersecting a first threshold voltage during said sampling window, performing a second integration function by enabling a second current source that produces a predetermined reference current and coupling said second current source to said integration capacitor so that both said first and second current sources are coupled to said integration capacitor to produce a second ramp voltage portion, wherein said reference current is greater than said first current and said ramp voltage during said second ramp voltage portion has a slope opposite in direction to said first ramp voltage portion;
- d. at least in part in response to said second ramp voltage portion intersecting a second threshold voltage, disabling said second current source;
- and
- e. counting all clock pulses produced by a clock with a first counter while said second current source is enabled to produce a digital value indicative of the magnitude of said analog input signal.
3 more elements
An analog to digital converter for producing a digital representation of an analog input signal comprising:
- a. a clock operative to produce successive clock cycles;
- b. a timer in communication with said clock and operative in response to a first control signal, to produce a timing signal that defines a sampling window having a time interval corresponding to a plurality of clock cycles, said sampling window having a window beginning and a window end;
- c. an integration capacitor;
- d. a first current source that produces a first current that is proportional to said analog input signal, said first current source coupleable to and cooperative with said integration capacitor and operative at least in part in response to said window beginning to produce a ramp voltage on said integration capacitor, wherein said ramp voltage has a starting voltage at the beginning of said sampling window and said ramp voltage generally has a first slope of a first direction during a first ramp voltage portion, wherein said first current source is disabled at the end of said sampling window;
- e. a second current source for providing a fixed predetermined reference current that is greater than a largest possible value of said first current in said analog to digital converter, said second current source coupleable to said integration capacitor and cooperative with said first current source and said integration capacitor to produce a second ramp voltage portion having a slope opposite in direction to said first ramp voltage portion;
- f. control logic responsive at least in part to said first ramp voltage portion intersecting a first threshold voltage during said sampling window, for enabling said second current source to produce the second ramp voltage portion having a slope opposite in direction to said first ramp voltage portion, said control logic being further operative, at least in part in response to said second ramp voltage portion intersecting a second threshold voltage, to disable said second current source during said sampling window;
- and
- g. a first counter operative to count clock cycles produced by said clock while said second current source is enabled to produce a digital value in said first counter at an end of said analog to digital conversion that is indicative of a magnitude of said analog input signal.
5 more elements
The analog to digital converter of claim method of claim wherein said control logic is further operative to:
- leave said second current source enabled to produce a third ramp voltage portion that intersects said second threshold voltage if said second current source is enabled at the end of said sampling window and an ending ramp voltage at the end of said sampling window is not between said starting voltage and said second threshold voltage;
- and
- disable said second current source in response at least in part to said third ramp voltage portion intersecting said second threshold voltage.
Dependencies are inferred from the claim text.