Sending and/or receiving serial data with bit timing and parallel data conversion

A deserializer arranged to receive a data word bit by bit, the deserializer comprising:

• a serial input port for receiving the data word bit by bit;
• a register for storing the data word bits, the register having a data input and a control input;
• means for connecting the serial input port to the register data input;
• a pulse generator receiving port for receiving pulses that defines the data word bits;
• means for connecting the received pulses to the control input wherein the data word bits are serially received and stored in the register, and
• means for detecting at least two bits added to the data word bits, wherein the added two bits always include a logic one and a logic zero in any order, and further wherein the signals on the pulse generator receiving port stay at a constant logic level during the receipt of the at least two added bits.

A serializer/deserializer for sending a data word out bit by bit and for receiving a data word bit by bit the serializer/deserializer comprising:

• a first register for holding the data word, the first register having at least one data output and a first control input;
• an output data port for serially outputting the data word bits by bit;
• means for connecting the first register at least one data output to the output data port;
• a pulse generator free of external timing reference;
• means for connecting the pulse generator to the first control input after a data word has been loaded into the first register, wherein the data word bits are serially output in response to the pulse generator;
• means for adding at least two boundary bits to the serially output data word bits, wherein the added at least two bits always include a logic one and the logic zero in any order, find further wherein the means for connecting the pulse generator to the first control input includes means for holding the signal at the control input at a constant logic level during the outputting of the at least two added bits;
• a serial input port for receiving the data word bit by bit;
• a second register for storing the data word bits, the second register having a data input and a control input;
• means for connecting the serial input port to the second register data input;
• a pulse generator receiving port for receiving pulses that defines the data word bits;
• means for connecting the received pulses to the control input, wherein the data word bits are serially received and stored in the second register, and
• means for detecting at least two bits added to the data word bits, and further wherein the signals on the pulse generator receiving port stay at a constant logic level during the receipt of the at least two added bits.

A process for serializing and sending a data word out bit by bit, the process comprising the steps of:

• holding the data word in a the register having at least one data output and a control input;
• connecting the data output to the output data port;
• generating pulses free of external timing reference;
• connecting the pulse generator to the control input after a data word has been loaded into the register, wherein the data word bits are serially output bit by bit;
• outputting signals from the pulse generator to define the serially output data word bits, and
• adding two boundary bits to the serially output data word bits, wherein the added two bits always include a logic one and a logic zero in any order;
• and
• maintaining the pulse generator output at a constant logic level during the outputting of the two added bits.

A process for receiving and deserializing a data word bit by bit, the process comprising the steps of:

• receiving the data word bit by bit via a serial input port;
• connecting the serial input port to the register data input;
• storing the data word bits in a register having a data input and a control input;
• receiving pulses that defines the data word bits;
• connecting the received pulses to the control input, wherein the data word bits are serially received and stored in the register;
• and
• detecting two bits added to the data word bits, wherein the added two bits always include a logic one and a logic zero in any order;
• and
• detecting signals on the pulse generator receiving port that remain at a constant logic level during the receipt of the two added bits.

A process for serializing and deserializing a data word sent out bit by bit and received bit by bit, the process comprising:

• holding the data word in a first register having at least one data output and a control input;
• connecting the data output to the output data port;
• generating pulses free of external timing reference;
• connecting the pulse generator to the control input after a data word has been loaded into the first register, wherein the data word bits are serially output bit by bit;
• outputting signals from the pulse generator to define the serially output data word bits;
• adding two boundary bits to the serially output data word bits, wherein the added two bits always include a logic one and a logic zero in any order;
• maintaining the pulse generator output at a constant logic level during the outputting of the two added bits;
• receiving the data word bit by bit via a serial input port;
• connecting the serial input port to a second register data input;
• storing the data word bits in the second register having a data input and a control input;
• receiving pulses that defines the data word bits;
• and
• connecting the received pulses to the control input, wherein the data word bits are serially received and stored in the second register;
• and
• detecting at least two bits added to the data word bits and that the signal on the pulse generator receiving port stay at a constant logic level during the receipt of the at least two added bits.