US 7,064,621 B2 · Synchronous clock generation circuit capable of ensuring wide lock-in range and attaining lower jitter · patentgrep

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Abstract

At a first step, in a synchronous clock generation circuit, the number of delay stages serving as a digital PLL circuit is increased/decreased, and an oscillation circuit performs an oscillation operation when an optimal number of delay stages is set. Thereafter, in an operation at a second step, a control voltage is controlled with the optimal number of delay stages being set for serving as an analog PLL circuit, thereby attaining a lock-in state. As the lock-in state is finally maintained under analog control, an excellent jitter characteristic can be obtained. Thus, ensuring a lock-in range that has been a problem in the analog PLL circuit is solved by varying the number of delay stages in the operation at the first step, and a high jitter characteristic that has been a problem in a digital PLL circuit can be solved by analog control in the operation at the second step.

Claims18

Dependent claims

A synchronous clock generation circuit, comprising:

an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information;
and
a control circuit;
wherein
said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and
after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value;
and wherein
said oscillation circuit includes
a plurality of delay circuits connected in series,
a selection circuit selecting one of outputs from said plurality of delay circuits as a selected output in accordance with said digital control information, and
an inversion delay circuit inverting said selected output and providing the inverted selected output to an input of a delay circuit at a first stage among said plurality of delay circuits, and
at least one of said plurality of delay circuits and said inversion delay circuit has a delay amount varied in accordance with said analog control information.

9 more elements

A synchronous clock generation circuit, comprising:

an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information;
and
a control circuit;
wherein
said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and
after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value;
and wherein
said oscillation circuit includes
a ring oscillator having an oscillation frequency varied in accordance with a first control voltage, and
a voltage control circuit outputting said first control voltage in accordance with said analog control information, and
said voltage control circuit includes
a first field effect transistor of a first conductivity type, diode-connected between a node receiving a first power supply potential and a first internal node outputting said first control voltage,
a second field effect transistor of a second conductivity type connected between said first internal node and a second internal node and receiving a control voltage in accordance with said analog control information at its gate, and
a resistor circuit connected between said second internal node and a node receiving a second power supply potential and having a resistance value across opposing ends varied in a discrete manner in accordance with said digital control information.

11 more elements

A synchronous clock generation circuit, comprising:

an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information;
and
a control circuit;
wherein
said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and
after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value;
and wherein
said oscillation circuit includes
a voltage control circuit outputting a first control voltage in accordance with said analog control information, and
a ring oscillator having an oscillation frequency varied in accordance with said first control voltage, and
said ring oscillator includes an odd number of inversion delay circuits having a driving power varied in a discrete manner in accordance with said digital control information and connected in series so as to form a ring.

8 more elements

A synchronous clock generation circuit, comprising:

an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information;
and
a control circuit;
wherein
said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and
after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value;
and wherein
said oscillation circuit includes
a plurality of differential amplifier circuits each outputting two complementary output signals in response to two complementary input signals and connected in series,
a selection circuit selecting one of said plurality of differential amplifier circuits in accordance with said digital control information,
a voltage control circuit outputting a first control voltage in accordance with said analog control information, and
an inversion delay circuit inverting two complementary output signals from the differential amplifier circuit selected by said selection circuit respectively and providing two complementary inverted output signals to an input of a differential amplifier circuit at a first stage among said plurality of differential amplifier circuits,
said inversion delay circuit includes
a first field effect transistor receiving said first control voltage at its gate and restricting a power supply current,
a first resistance element and a second field effect transistor connected in series between a drain of said first field effect transistor and a power supply node, and
a second resistance element and a third field effect transistor connected in series between the drain of said first field effect transistor and the power supply node, and
gates of said second and third field effect transistors receive two complementary output signals from the differential amplifier circuit selected by said selection circuit respectively.

14 more elements

A synchronous clock generation circuit, comprising:

an oscillation circuit providing an output clock signal having an oscillation frequency varied in a discrete manner in accordance with digital control information and providing said output clock signal having an oscillation frequency continuously varied in accordance with analog control information;
and
a control circuit;
wherein
said control circuit temporarily fixes said analog control information to a prescribed value and controls said digital control information in accordance with said output clock signal so as to achieve a first lock state in which a phase difference between said output clock signal and an input clock signal attains at most a first prescribed value, and
after said first lock state is established, said control circuit fixes said digital control information and controls said analog control information in accordance with said oscillation frequency so as to achieve a second lock state in which a phase difference between said output clock signal and said input clock signal attains at most a second prescribed value;
and wherein
said oscillation circuit includes
a plurality of differential amplifier circuits connected in series and outputting two complementary output signals in response to two complementary input signals,
a voltage control circuit outputting a first control voltage in accordance with said analog control information, and
an inversion delay circuit inverting two complementary output signals from the delay circuit selected by said selection circuit respectively and providing two complementary inverted output signals to an input of a differential amplifier circuit at a first stage among said plurality of differential amplifier circuits,
said inversion delay circuit includes
a first field effect transistor receiving said first control voltage at its gate and restricting a power supply current,
a first resistor circuit and a second field effect transistor connected in series between a drain of said first field effect transistor and a power supply node, and
a second resistor circuit and a third field effect transistor connected in series between the drain of said first field effect transistor and the power supply node,
gates of said second and third field effect transistors receive two complementary output signals from the differential amplifier circuit selected by said selection circuit respectively, and
said first and second resistor circuits have a resistance value varied in a discrete manner in accordance with said digital control information.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/899,070Filed 27 Jul 2004
Priority: JP 2003-29293813 Aug 2003
Published: US 2005/0046497 A13 Mar 2005
Granted: 20 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

Family

US 2005/0046497 A1Pre-grant publication · published 3 Mar 2005
US 7,064,621 B2This patent

From the US filing history. Foreign family members aren’t listed.

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