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US 7,064,620 B1Granted
Sequential VCO phase output enabling circuit
AssigneeAltera Corporation
InventorsKang-Wei Lai, Greg Starr
Life of this patent
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Abstract
Circuits, methods, and apparatus that provide a sequential start-up of outputs of an oscillator following a power-up or restart. The outputs are gated by enable signals. These enable signals are derived sequentially, the first in a series being triggered by a specific output of the oscillator.
Claims20
A voltage controlled oscillator comprising:
- a first VCO element having an output;
- a second VCO element having an input and an output, the input coupled to the output of the first VCO element;
- a first gated circuit having an input and an output, the input coupled to the output of the first VCO element;
- a second gated circuit having an input and an output, the input coupled to the output of the second VCO element;
- and
- a first logic circuit configured to receive a VCO enable signal, the output of the first VCO element, and the output of the second VCO element, and further configured to provide a first output enable signal to the first gated circuit and a second output enable signal to the second gated circuit.
3 more elements
A method of enabling outputs of a voltage controlled oscillator comprising:
- receiving a VCO enable signal;
- receiving a first VCO output signal;
- receiving a second VCO output signal, the second VCO output signal phase shifted from the first VCO output signal;
- and
- retiming the VCO enable signal with the first VCO output signal to generate a first VCO output enable signal.
2 more elements
A voltage controlled oscillator comprising:
- means for generating a plurality of clock outputs including a first clock output and a second clock output, the first and second clock outputs shifted in phase relative to each other;
- means for gating the first clock output and the second clock output;
- means for receiving a VCO enable signal;
- and
- means for retiming the VCO enable signal to the first clock output to generate a first gating signal,
- wherein the first gating signal controls the means for gating the first clock output.
3 more elements
Dependencies are inferred from the claim text.