PLL with swappable tuning loops

#The present application is related to commonly-assigned and co-pending application Ser. No.10/673,803, entitled PLL WITH MULTIPLE TUNING LOOPS, and filed concurrently herewith.

#A Phase-Locked Loop (PLL) may be used to generate an output signal having a desired frequency, such as a clock signal. A PLL might “lock” to the desired frequency by receiving its output signal via a feedback loop, determining a difference between the output signal and a reference signal, and changing its transfer function in order to reduce the difference.

#PLL design often involves trade-offs between tuning range and noise immunity. More specifically, some conventional PLL designs provide a wide range of output frequencies while exhibiting poor noise immunity, while others provide a narrow range of output frequencies while exhibiting good noise immunity. PLL designs that may provide suitable response characteristics within a range of normal operating frequencies are desired.

#FIG. 1 is a block diagram of a PLL according to some embodiments.

#FIG. 2 is a flow diagram of a process for tuning a PLL according to some embodiments.

#FIG. 3 is a schematic diagram of a switch capacitor circuit according to some embodiments.

#FIG. 1 is a block diagram of PLL 100 according to some embodiments. PLL 100 comprises phase-frequency detector 110, charge pump 120, switch capacitor circuit 130 and associated switch 135, main loop circuit 140 and associated switch 145, VCO 150, and feedback divider 160. PLL 100 may generate an oscillating signal fout having a frequency that is based on a reference frequency represented by input signal fin. In some embodiments, the reference frequency is equal to the frequency of input signal fin, and PLL 100 locks the frequency of fout to N(f(fin)).

#Generally, according to some embodiments, switch capacitor circuit 130 is coupled to control signal Icontrol by closing switch 135. Next, an output capacitance of switch capacitor circuit 130 is determined to be oscillating, and switch 135 is opened to uncouple switch capacitor circuit 130 from control signal Icontrol to set a first output capacitance of switch capacitor circuit 130. Main loop circuit 140 is then coupled to control signal Icontrol by closing switch 145. The foregoing process may provide a wider tuning range and better response over a target range of frequencies than previously available. Details of the process according to some embodiments will be set forth below.

#Returning to the elements of PLL 100, detector 110 may determine a difference between the frequency or phase of two signals and transmit a signal to charge pump 120 based on the determined difference. Charge pump 120 generates and transmits control signal Icontrol based on the signal received from detector 110. In some embodiments, detector 110 receives reference signal fin having frequency (f(fin)), and signal fout/N having frequency f(fout)/N. In this regard, feedback divider 160 may operate to divide the frequency or phase of signal fout by N prior to transmitting the signal to detector 110. Detector 110 compares the frequencies of the two received signals and transmits a signal indicating the results of the comparison to charge pump 120.