US 7,064,616 B2 · Multi-stage numeric counter oscillator

Abstract

A numeric counter oscillator is disclosed comprising a quotient accumulator and a remainder accumulator. The quotient accumulator has a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output. The output is adapted for transmitting an output value OUT representing an accumulated quotient sum. The multi-bit output increments by a predetermined amount in response to each reference clock period. The remainder accumulator comprises programmable inputs for receiving respective REMAINDER and DIVISOR values, a a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer. The remainder accumulator further comprises a comparator having a first input for receiving a programmed divisor value, and a second input for receiving the remainder accumulator multi-bit output. The comparator is operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output reaches the predefined integer value.

Claims26

Dependent claims

A numeric counter oscillator comprising:

a quotient accumulator, the quotient accumulator having a programmable input for receiving a QUOTIENT value, a reference clock input and a multi-bit output, the output adapted for transmitting an output value OUT representing an accumulated quotient sum, the multi-bit output incrementing in response to each reference clock period;
a remainder accumulator, the remainder accumulator having programmable inputs for receiving respective REMAINDER and DIVISOR values, a reference clock input and a multi-bit output representing an accumulated digital remainder sum less than a predefined digital integer, the remainder accumulator further comprising:
a) an arithmetic circuit having an output representing accumulated remainder values;
and
b) circuitry having a first input for receiving a programmed divisor value, and a second input for receiving the output of the arithmetic circuit, the circuitry operative to generate an increment carry signal for application to the quotient accumulator when the remainder multi-bit output of the arithmetic circuit exceeds a value dependent on the programmed divisor value.

2 more elements

A variable frequency clock generator, comprising:

a) a numeric counter oscillator, comprising:
i) a first control input;
ii) a second control input;
iii) a clock input;
iv) a digital output having a value that changes at a plurality of times correlated to the clock input, wherein at a first subset of said times, the value of the digital output changes in proportion to the value of the first control input and, at a second subset of said plurality of times, the value of the digital output changes in proportion to the value of the first control input combined with an adjustment value, the timing of the second subset of said plurality of times depending on the value of the second control input;
b) a conversion circuit having an input and a digital output, the input coupled to the output of the numeric counter oscillator and the digital output of the conversion circuit taking on a value dictated by the input;
c) a digital to analog converter having a digital input coupled to the digital output of the conversion circuit and an analog output;
and
d) a conditioning circuit having an analog input connected to the output of the digital to analog circuit and an output providing a second clock with a frequency that varies in relation to the value of the first control input and/or the second control input.

6 more elements

Dependencies are inferred from the claim text.

Multi-stage numeric counter oscillator

Life of this patent

Multi-stage numeric counter oscillator

Life of this patent

Abstract

Claims26