High voltage, low-offset operational amplifier with rail-to-rail common mode input range in a digital CMOS process

An operational amplifier comprising the following:

• a positive input terminal;
• a negative input terminal;
• a first current source;
• a second current source;
• a first differential pair coupled to the first current source, the first differential pair including a first field effect transistor and a second field effect transistor, each of the first and second field effect transistors having a source, drain, gate and bulk terminal, wherein the gate terminal of the first field effect transistor is coupled to the positive input terminal and the gate terminal of the second field effect transistor is coupled to the negative input terminal;
• a second differential pair coupled to the second current source, the second differential pair including a first depletion type field effect transistor and a second depletion type field effect transistor, each of the first and second depletion type effect transistors having a source, drain, gate and bulk terminal, wherein the gate terminal of the first depletion type field effect transistor is coupled to the negative input terminal and the gate terminal of the second depletion type field effect transistor is coupled to the positive input terminal;
• a third field effect transistor having a source, drain, gate and bulk terminal, wherein the source terminal of the third field effect transistor is coupled to the drain terminal of the first depletion type field effect transistor, the third field effect transistor being a high voltage field effect transistor;
• and
• a fourth field effect transistor having a source, drain, gate and bulk terminal, wherein the source terminal of the fourth field effect transistor is coupled to the drain terminal of the second depletion type field effect transistor, the fourth field effect transistor being a high voltage field effect transistor, the gate terminal of the fourth field effect transistor being coupled to the gate terminal of the third field effect transistor and to a voltage source.

An output stage of an operational amplifier comprising the following:

• a first voltage source;
• an output terminal;
• a first field effect transistor having a source, drain, gate and bulk terminal, the source terminal being coupled to the first voltage source, the first field effect transistor not being a high voltage field effect transistor;
• a second field effect transistor having a source, drain, gate and bulk terminal, the source terminal of the second field effect transistor being coupled to the first voltage source, the gate terminal of the second field effect transistor being coupled to the gate terminal of the first field effect transistor and to the drain terminal of the first field effect transistor, the second field effect transistor not being a high voltage field effect transistor;
• a first high voltage field effect transistor having a source, drain, gate and bulk terminal, the source terminal of the first high voltage field effect transistor being coupled to the drain terminal of the first field effect transistor;
• and
• a second high voltage field effect transistor having a source, drain, gate and bulk terminal, the source terminal of the second high voltage field effect transistor being coupled to the drain terminal of the second field effect transistor, the drain terminal of the second high voltage field effect transistor being coupled to the output terminal, the gate terminal of the second high voltage field effect transistor being coupled to the gate terminal of the first high voltage field effect transistor and to a second voltage source.