Reference voltage generating circuit using active resistance device

A reference voltage generating circuit comprising:

• a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal, the current mirror circuit being operated in response to a voltage level of the second current path;
• a reference voltage output node for providing a reference voltage, the reference voltage output node being located on the second current path;
• an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device;
• and
• a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region, wherein the voltage supply circuit includes a PMOS transistor and a plurality of NMOS transistors, wherein the enable voltage is determined by the NMOS transistors and obtained at a node between the PMOS transistor and the plurality of NMOS transistors,
• wherein a gate of the PMOS transistor is connected to a drain of a first PMOS transistor formed on the first current path, a source of the PMOS transistor receives an externally applied voltage and is connected to a back gate of the PMOS transistor, and a drain of the PMOS transistor is connected to a drain and a gate of a first NMOS transistor of the plurality of NMOS transistors.

A reference voltage generating circuit comprising:

• a current mirror circuit having first and second MOS transistors, sources of the first and second MOS transistors receiving an externally applied voltage, a gate of the first MOS transistor being connected to a gate of the second MOS transistor and to a drain of the first MOS transistor;
• a current control circuit having third and fourth MOS transistors, a drain of the third MOS transistor being connected to the drain of the first MOS transistor, a drain of the fourth MOS transistor being connected to a gate of the third MOS transistor and a drain of the second MOS transistor, a source of the fourth MOS transistor being connected to a ground, and a reference voltage being provided on a node between the drain of the second MOS transistor and the drain of the fourth MOS transistor;
• an active resistance circuit having a fifth MOS transistor, a drain of the fifth MOS transistor being connected to a gate of the fourth MOS transistor and a source of the third MOS transistor, a source of the fifth MOS transistor being connected to the ground, and a gate of the fifth MOS transistor receives a control voltage higher than a voltage between the drain and source of the fifth MOS transistor so that the fifth MOS transistor is operated in a linear region;
• and
• a voltage supply circuit having a PMOS transistor and a set of NMOS transistors, wherein the voltage supply circuit supplies an enable voltage to the fifth MOS transistor, wherein the enable voltage as the control voltage is determined by the set of NMOS transistors,
• wherein a gate of the PMOS transistor is connected to the drain of the first MOS transistor, a source of the PMOS transistor receives the externally applied voltage and is connected to a back gate of the PMOS transistor, a drain of the PMOS transistor is connected to a drain and gate of a first NMOS transistor of the set of NMOS transistors which are connected in series between the PMOS transistor and the ground, and the control voltage is provided from a node between the PMOS transistor and the first NMOS transistor of the set of NMOS transistors to the gate of the fifth MOS transistor.