Radio frequency CMOS buffer circuit and method

A circuit comprising:

• a signal source having an output terminal for providing a time-varying signal having a peak-to-peak signal swing equal to a first voltage;
• and
• a buffer coupled to first and second power supply voltage terminals for respectively receiving first and second power supply voltages thereon, and having an input terminal coupled to said output terminal of said signal source, and an output terminal;
• a difference between said first and second power supply voltages being equal to a second voltage that is less than said first voltage;
• wherein said buffer comprises:
• a capacitor having a first terminal coupled to said output terminal of said signal source, and a second terminal;
• a first transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said second terminal of said capacitor, and a second current electrode far providing an output signal of said buffer;
• a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode coupled to said second terminal of said capacitor, and a second current electrode coupled to said second power supply voltage terminal;
• wherein a capacitance of said capacitor is chosen such that a peak-to-peak voltage swing at said control electrodes of said first and second transistors is less than or equal to said second voltage, and wherein the capacitance of the capacitor is greater than a combined parasitic capacitance of the first transistor and the second transistor.

A method of buffering an input signal having a peak-to-peak voltage

• equal to a first voltage comprising the steps of:
• capacitively dividing the first voltage using a capacitive divider formed by a capacitor having a first terminal for receiving the input signal and a second terminal in series with a parasitic capacitance formed by control electrodes of first and second transistors to provide a second signal at said second terminal of said capacitor having a peak-to-peat voltage equal to a second voltage, wherein a capacitance of said capacitor is mater than the parasitic capacitance;
• and
• buffering said second signal using a buffer including said first and second transistors driven by a power supply voltage that is less than said first voltage and greater than or equal to said second voltage.