US 7,064,591 B1 · Coarse tuning for fractional-N synthesizers

Abstract

An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer such that the phase lock loop operates in an integer division mode during coarse tuning, thereby eliminating jitter due to fractional-N operation during coarse tuning. The coarse tuning circuit includes divide value generation circuitry that provides an integer divide value to an N divider of the PLL during coarse tuning and a fractional-N sequence to the N divider during fractional-N operation.

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Claims32

Dependent claims

A fractional-N frequency synthesizer comprising:

a phase lock loop (PLL);
and
coarse tuning circuitry coupled to the PLL and adapted to control the PLL such that the PLL operates in an integer division mode during coarse tuning and a fractional-N division mode during normal operation, wherein the coarse tuning circuitry comprises divide value generation circuitry adapted to:
provide an integer divide value to a divider of the PLL when operating in the integer division mode;
and
provide a fractional sequence of divide values to the divider of the PLL when operating in the fractional-N division mode,
wherein the PLL comprises a controlled oscillator (CO) and the coarse tuning circuitry further comprises:
an M divider adapted to divide a reference signal from the PLL by a factor M to provide an divided reference signal;
and
tuning logic adapted to:
compare a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from the CO divided by the integer divide value;
and
provide a tuning curve control signal to select a tuning curve for a CO of the PLL based thereon to effect coarse tuning of the CO.

10 more elements

A method for coarse tuning a fractional-N frequency synthesizer comprising:

providing an integer divide value to a divider of a phase lock loop (PLL) during coarse tuning, thereby controlling the PLL such that the PLL operates in an integer division mode during coarse tuning;
providing a fractional sequence of divide values to the divider of the PLL during normal operation, thereby controlling the PLL such that the PLL operates in a fractional-N division mode during normal operation;
dividing a reference signal from the PLL by a factor M to provide a divided reference signal;
comparing a frequency of the divided reference signal and a frequency of a divided controlled oscillator (CO) signal during coarse tuning, wherein the divided CO signal is a CO signal from a CO of the PLL divided by the integer divide value;
and
providing a tuning curve control signal to select a tuning curve for the CO of the PLL based thereon to effect coarse tuning of the CO.

3 more elements

Dependencies are inferred from the claim text.

Description4,772 words

Summary651 words

#The present invention relates to a fractional-N frequency synthesizer, and more particularly to improved coarse tuning for a fractional-N frequency synthesizer.

#Frequency synthesizers are used in many systems, including microprocessors and radio frequency (RF) communication systems. Frequency synthesizers of the phase locked loop (PLL) type contain controlled oscillators (CO) that are typically current controlled oscillators (ICO) or voltage controlled oscillators (VCO). The output of the CO is often used as an injection signal for an RF mixer or in a microprocessor clock system. The frequency synthesizer controls the CO such that its frequency or period is approximately equal to that of a stable frequency reference multiplied by a predetermined ratio. In many applications, there is a need to compensate for process and environmental variations that affect synthesizer performance. The prior art contains many systems, known as coarse tuning systems, that compensate for variations in the CO's frequency tuning range or center frequency by performing a coarse tuning of the tunable elements in the CO. These systems have been developed for integer-N synthesizers where the divided CO signal used for feedback to the phase detector has a steady period when the CO's output frequency is not changing.

#The use of fractional-N synthesizers provides reduced lock times for the synthesizer's phase lock loop (PLL) and improves noise performance, but introduces significant jitter on the divided CO signal. Even with a constant CO output frequency, the divider modulus, and therefore the period of the divided CO signal, is varied from one output clock cycle to the next to provide a desired average fractional modulus over a period of time. The resulting jitter on the divided CO signal significantly reduces the accuracy of existing techniques for calibrating and tuning the CO. Accordingly, there is a need for a technique to reduce the impact of jitter on the divided CO signal and provide accurate calibration or coarse tuning of a CO in a fractional-N synthesizer in a cost-effective and efficient manner.

Brief description of the drawings9 figures

#The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the invention, and together with the description serve to explain the principles of the invention.

#FIG. 1 illustrates a fractional-N frequency synthesizer according to one embodiment of the present invention;

#FIG. 2A illustrates a resonant tank of the voltage controlled oscillator of the fractional-N synthesizer of FIG. 1 according to one embodiment of the present invention;

Detailed description3,929 words

#The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention and illustrate the best mode of practicing the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

#FIG. 1 illustrates a fractional-N frequency synthesizer 10 according to the present invention. During coarse tuning, the frequency synthesizer 10 operates in an integer divide mode, thereby eliminating all frequency error due to jitter. Once coarse tuning is performed, the frequency synthesizer switches to normal operation in a fractional-N division mode and locks to the desired frequency.

#With reference to FIG. 1, the fractional-N frequency synthesizer 10 includes a fractional-N phase lock loop (PLL) 12 and coarse tuning circuitry 14. The PLL 12 generates a desired frequency for the output signal, FVCO, 16, of a voltage controlled oscillator (VCO) 18. In traditional fashion, the output signal FVCO 16 is also provided to divider circuitry 20 to divide the output signal FVCO by a factor N to produce a divided VCO signal Fv, which is fed to one of two inputs of a phase detector 22.

Facts

Application

10/901,669Filed 29 Jul 2004 · us provisional application

Priority

11 May 2004

Granted

20 Jun 2006

Term ended

14 Sep 2024

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment, including 47 days of adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification6 codes

H03L 7/193
A time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number:…
H03L 7/103
The additional signal being directly applied to the controlled loop oscillator: the additional signal being a digital signal
H03L 7/1974
A time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider…: for…
H03J 2200/10
Indexing scheme relating to tuning resonant circuits and selecting resonant circuits: tuning of a resonator by means of digitally controlled…

Timeline

11 May 2004Priority claimedParent application 60/569,900
29 Jul 2004Application filedUS 10/901,669
29 Jul 2004Assigned to Rf Micro Devices, Inc.assignment of assignor's interest
20 Jun 2006GrantedUS 7,064,591 B1
19 Mar 2013Assigned to Bank of America, N.A., AS Administrative Agentnotice of grant of security interest in patents
30 Mar 2015Assigned to Rf Micro Devices, Inc.termination and release of security interest in patents (recorded 3/19/13 at reel/frame 030045/0831)
16 Jun 2016Assigned to Qorvo US, Inc.merger
14 Sep 2024Term endedEstimated, includes 47 days of adjustment

Coarse tuning for fractional-N synthesizers

Life of this patent

Coarse tuning for fractional-N synthesizers

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims32

Description4,772 words

Drawings

Classification6 codes

Life of this patent

Description4,772 words