Output Buffer

A low-noise buffer for a digital logic signal, comprising:

• an analog amplifier;
• a converter circuit operative to convert the digital logic signal to a ramp signal provided as an input to the analog amplifier, the ramp signal having a slope determined by a bias current and an input capacitance of the analog amplifier;
• and
• a bias circuit operative to generate the bias current in a manner ensuring that the bias current varies as the input capacitance of the analog amplifier varies, such that the slope of the ramp signal remains substantially constant,
• wherein the ramp circuit comprises:
• a first switched current mirror operative to generate current of one polarity when the digital logic signal has a first logic value;
• and
• a second switched current mirror operative to generate current of the opposite polarity when the digital logic signal has a second logic value.

A low-noise buffer for a digital logic signal, comprising:

• an analog amplifier;
• a converter circuit operative to convert the digital logic signal to a ramp signal provided as an input to the analog amplifier, the ramp signal having a slope determined by a bias current and an input capacitance of the analog amplifier;
• and
• a bias circuit operative to generate the bias current in a manner ensuring that the bias current varies as the input capacitance of the analog amplifier varies, such that the slope of the ramp signal remains substantially constant,
• wherein the bias circuit comprises a switched-capacitor across which a predetermined reference voltage is placed to generate the bias current, the switched-capacitor including a capacitor having capacitance that varies as the input capacitance of the analog amplifier varies due to variations in the manufacturing process of the buffer.