Input buffer circuit including reference voltage monitoring circuit

An input buffer system comprising:

• a reference voltage monitoring circuit, the reference voltage monitoring circuit having an input coupled to a reference voltage and an output. the reference voltage monitoring circuit generating a signal at the output in response to a change in the reference voltage;
• at least first and second buffer circuits, each buffer circuit comprising:
• a differential amplifier, the differential amplifier having an output, a first input coupled to the reference voltage, a second input coupled to an input voltage. and a current source, the differential amplifier generating a signal at the output in response to a difference between the reference voltage and the input voltage;
• a buffering inverter, the buffering inverter having an input connected to the output of the differential amplifier, the buffering inverter generating an output in response to the output of the differential amplifier and the output of the reference voltage monitoring circuit, wherein the buffering inverter includes first and second buffering inverter transistors, a drain of the first buffering inverter transistor being connected to a drain of a second buffering inverter transistor, a source of the first buffering inverter transistor being connected to the output of the reference voltage monitoring circuit, a source of the second buffering inverter transistor being connected to ground;
• a driver circuit, including a comparator, that receives at a first input the output from the reference voltage monitoring circuit and having an output that is connected to a second input of the comparator and to each buffering inverter, wherein a signal at the output of the comparator varies in relation to variations in the reference voltage so as to in turn vary a logic threshold voltage of the buffering inverter in each of the at least first and second buffer circuits.

A method of controlling a plurality of input buffers and matching signal duty cycles in response to a change in a reference voltage, comprising:

• providing at least two buffer circuits, each buffer circuit including a differential amplifier, the differential amplifier having a reference voltage as an input and a current source, a buffering inverter, the buffering inverter having an output of the differential amplifier as an input;
• and
• providing a reference voltage monitoring circuit, the reference voltage monitoring circuit including two transistors and a second current source, wherein the reference voltage monitoring circuit has a structure similar to a portion of the structure of the differential amplifier, and
• providing a driver circuit, the driver circuit including a comparator, the driver circuit receiving an output from the reference voltage monitoring circuit,
• wherein an output of the reference voltage monitoring circuit is connected to the buffering inverter so as to minimize an effect of a variation in the value of the reference voltage on signal propagation delays.

A buffer circuit, comprising:

• differential amplifying means, the differential amplifying means including a plurality of transistors, a current source, a first input coupled to a reference voltage and a second input coupled to an input voltage and an output, the differential amplifying means generating a signal at the output in response to a difference between the reference voltage and the input voltage;
• reference voltage monitoring means, the reference voltage monitoring means for monitoring a reference voltage as the reference voltage varies, the reference voltage monitoring means generating a signal at an output in response to a change in the reference voltage, the structure of the reference voltage monitoring means structure being similar to a portion of the structure of the differential amplifying means;
• and
• at least one buffering means, the buffering means including a plurality of transistors, the buffering means having an input connected to the output of the differential amplifying means and generating an output in response to the output of the differential amplifying means and the output of the reference voltage monitoring means, wherein the buffering means includes first and second buffering transistors, a drain of the first buffering transistor being connected to a drain of a second buffering transistor, a source of the first buffering transistor being connected to the output of the reference voltage monitoring means, a source of the second buffering transistor being connected to ground;
• and
• wherein the reference voltage monitoring means includes first and second transistors and a second current source, a drain of the first transistor being connected to a drain of the second transistor, a abate and a drain of the first transistor being connected to each other, a gate of the second transistor being connected to the reference voltage, a source of the transistor being connected to the second current source;
• and
• wherein the output of the reference voltage monitoring means being coupled as an input to the at least one buffering means so as to vary a logic threshold voltage of the buffering means to minimize an effect of a variation in the value of the reference voltage on signal propagation delay times.