P-domino output latch with accelerated evaluate path

A P-domino latch circuit, comprising:

• P-logic, coupled to a first N-channel device at a pre-charged node, configured to evaluate a logic function based on at least one input data signal, said first N-channel device comprising:
• a gate for receiving said clock signal and a source and drain coupled between a ground voltage and said pre-charged node;
• latching logic, coupled and responsive to a clock signal and said pre-charged node, configured to control the state of a latch node based on the state of said pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of said clock signal, and configured to otherwise present a tri-state condition to said latch node, wherein keeper logic maintains the state of said latch node when said tri-state condition is presented, and wherein said keeper logic provides a complementary state of said latch node at a complementary latch node;
• and
• acceleration logic, coupled and responsive to said pre-charged node and said complementary latch node, wherein an output of said acceleration logic forms an output node providing an output signal, and wherein said acceleration logic is configured to control the state of said output node.

A method of providing an accelerated output in an P-domino latch circuit, comprising:

• pre-setting a pre-charged node while a clock signal is in a first logic state;
• coupling the pre-charged node to acceleration logic that forms an output node providing the accelerated output;
• dynamically evaluating a P-logic function to control the logic state of the first node when the clock signal transitions to a second logic state;
• latching a logic state of a latch node based on the logic state of the pre-charged node determined during an evaluation period beginning when the clock signal transitions to the second logic state and ending with the next corresponding transition of the clock signal to the first logic state;
• complementing the logic state of the latch node to provide a complementary latch node;
• and
• accelerating presentation of the accelerated output by responding to the state of the pre-charged node during the evaluation period.