Arbiters with preferential enables for asynchronous circuits
AssigneeSun Microsystems, Inc.
InventorsJo C. Ebergen, Ivan E. Sutherland, Bernard Tourancheau
Life of this patent
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Abstract
One embodiment of the present invention provides a circuit that preferentially grants requests. This circuit monitors at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with a corresponding enable signal. If any enable signal is asserted and only one request signal is asserted, the circuit asserts a grant signal associated with the asserted request signal. Otherwise, if a single enable signal is asserted and multiple request signals are asserted, the circuit preferentially asserts the grant signal of the request signal associated with the asserted enable signal.
Claims24
A method for preferentially granting requests in an asynchronous circuit, comprising;
- monitoring at least two inputs for request signals and at least two inputs for enable signals, wherein each request signal is associated with an enable signal;
- if any enable signal is asserted and only one request signal is asserted, asserting a grant signal associated with the asserted request signal;
- and
- if a single enable signal is asserted and multiple request signals are asserted, preferentially asserting the grant signal of the request signal associated with the asserted enable signal.
An asynchronous circuit for preferentially granting requests, comprising:
- at least two logic gates;
- wherein each logic gate accepts a request signal, at least two enable signals and at least one feedback signal as inputs and drives a single output signal;
- and
- wherein each logic gate includes a circuit element which preferentially grants the request signal for that gate when the enable signal associated with that request is asserted.
An apparatus for preferentially granting requests, comprising:
- at least two logic gates;
- wherein each logic gate accepts a request signal, at least two enable signals and at least one feedback signal as inputs and drives a single output signal;
- and
- wherein each logic gate includes a circuit element which preferentially grants the request signal for that gate when the enable signal associated with that request is asserted.
A computer system including an asynchronous circuit for preferentially granting requests, comprising:
- at least two logic gates;
- wherein each logic gate accepts a request signal, at least two enable signals and at least one feedback signal as inputs and drives a single output signal;
- and
- wherein each logic gate includes a circuit element which preferentially grants the request signal for that gate when the enable signal associated with that request is asserted.
Dependencies are inferred from the claim text.