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US 7,064,582 B2Granted
Output buffer strength trimming
AssigneeMicron Technology, Inc.
InventorsGirolamo Gallo, Giulio Marotta, Giovanni Naso
Life of this patent
Estimating the term…
Abstract
Apparatus and methods for adjusting the buffer strength of an output buffer to match its capacitive load use selectively enabled stages of a multiple stage output buffer. A user can opt for a default capacitive load, or adjust the strength by enabling one or more stages of the multiple stage output buffer.
Claims31
An output buffer, comprising:
- a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active;
- wherein each output stage comprises:
- a complementary metal oxide semiconductor (CMOS) structure having a p-channel MOS device and an n-channel MOS device;
- an AND gate having an output connected to a gate of the n-channel transistor, and having two inputs, an input connected to a data signal and another input connected to one of a plurality of enable signals;
- and
- an OR gate having an output connected to a gate of the p-channel transistor, and having two inputs, an input connected to the data signal and another input connected to a complement of the one of the plurality of enable signals;
- and
- a bank of latches, the bank of latches having an enable latch and two or more trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to the respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.
5 more elements
An output buffer, comprising:
- a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active;
- and
- an output buffer trim circuit, the trim circuit comprising:
- a bank of latches, the bank of latches having an enable latch and a plurality of trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to a respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.
1 more element
An output buffer, comprising:
- at least two parallel buffer stages, each stage activated upon receipt of a respective stage enable signal, the stages providing a range of output buffer strengths cumulatively to a total output buffer strength, wherein each output stage comprises:
- a pair of CMOS components, the first CMOS component connected to a non-volatile buffer strength signal, and the second CMOS component connected to a selectable variable buffer strength signal;
- and
- selection circuitry to select either the first CMOS component or the second CMOS component.
1 more element
An output buffer, comprising:
- at least two parallel buffer stages, each stage activated upon receipt of a respective stage enable signal, the stages providing a range of output buffer strengths cumulatively to a total output buffer strength, wherein each output stage comprises:
- a pair of CMOS components, the first CMOS component connected to a hard coded buffer strength signal, and the second CMOS component connected to a selectable buffer strength signal;
- and
- selection circuitry to select either the first CMOS component or the second CMOS component;
- wherein the selection circuitry comprises:
- a bank of latches, the bank of latches providing a plurality of enable signals, each enable signal for one of the second CMOS components of the plurality of the stages;
- wherein the bank of latches further comprises an enable latch to enable the plurality of enable signals.
4 more elements
An output buffer circuit, comprising:
- a first output buffer stage for providing an output buffer strength in response to a first stage enable signal;
- and
- at least one second output buffer stage, wherein each second output buffer stage is adapted to selectively provide additional buffer strength in response to a respective second stage enable signal, wherein each output stage comprises:
- a pair of CMOS components, the first CMOS component connected to a non-volatile buffer strength signal, and the second CMOS component connected to a selectable variable buffer strength signal;
- and
- selection circuitry to select either the first CMOS component or the second CMOS component.
3 more elements
An output buffer circuit, comprising:
- a plurality of output stages, each output stage selectable to provide a component of a total output buffer strength, each output stage comprising:
- a pair of CMOS components, the first CMOS component connected to a non-volatile buffer strength enable signal, and the second CMOS component connected to a selectable variable buffer strength enable signal;
- and
- selection circuitry to select either the first CMOS component or the second CMOS component.
1 more element
An output buffer circuit, comprising:
- a plurality of output stages, each output stage selectable to provide a component of a total output buffer strength, each output stage comprising:
- a pair of CMOS components, the first CMOS component connected to a hard coded buffer strength enable signal, and the second CMOS component connected to a selectable buffer strength enable signal;
- and
- selection circuitry to select either the first CMOS component or the second CMOS component;
- wherein the selection circuitry comprises:
- a bank of latches, the bank of latches providing a plurality of enable signals, each enable signal for one of the second CMOS components of the plurality of the stages;
- and
- wherein the bank of latches further comprises an enable latch to enable the plurality of enable signals.
5 more elements
An output buffer, comprising:
- a first stage and a second stage, the first and second stages parallel to each other, the first stage comprising:
- a first stage complementary metal oxide semiconductor (CMOS) structure having a p-channel MOS device and an n-channel MOS device;
- a first OR gate having an output connected to a gate of the p-channel transistor, and having two inputs, an input connected to a data signal and another input connected to an enable signal;
- and
- a first AND gate having an output connected to a gate of the n-channel transistor, and having two inputs, an input connected to the data signal and another input connected to the enable signal;
- the second stage comprising:
- a second stage CMOS structure having a p-channel MOS device and an n-channel MOS device;
- a second OR gate having an output connected to a gate of the p-channel transistor, and having two inputs, an input connected to a data signal and another input connected to an enable signal;
- and
- a second AND gate having an output connected to a gate of the n-channel transistor, and having two inputs, an input connected to the data signal and another input connected to the enable signal;
- and
- an output buffer trim circuit, the trim circuit comprising:
- a pair of trim latches, each storing a value representative of an enable signal, each trim latch connected to a respective enable input of one the first or the second stages to provide its enable signal to its respective output stage.
10 more elements
A trim circuit for an output buffer having multiple parallel connected output stages, comprising:
- a bank of latches, the bank of latches having an enable latch and a plurality of trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to a respective enable input of one of the output stages to provide its enable signal to its respective output stage;
- and
- selection circuitry to select either the bank of latches or a preprogrammed enable signal.
A memory device, comprising:
- an array of memory cells;
- a plurality of data lines for access to the memory cells;
- and
- an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer comprises:
- a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active;
- and
- a bank of latches, the bank of latches having an enable latch and two trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to the respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.
4 more elements
A memory device, comprising:
- an array of memory cells;
- a plurality of data lines for access to the memory cells;
- and
- an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer comprises a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active;
- and an output buffer trim circuit, the trim circuit comprising:
- a bank of latches, the bank of latches having an enable latch and a plurality of trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to a respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.
3 more elements
A system, comprising:
- a processor;
- a memory device coupled to the processor, the memory device comprising:
- an array of memory cells;
- a plurality of data lines for access to the memory cells;
- and
- an output buffer coupled between the array of memory cells and the plurality of data lines, wherein the output buffer comprises:
- a first stage and a second stage, the first and second stages having outputs connected parallel to one another, the first stage providing buffer strength when a first stage enable signal is active, and the second stage providing buffer strength when a second stage enable signal is active;
- and
- a bank of latches, the bank of latches having an enable latch and two trim latches, each trim latch storing a value representative of an enable signal, each trim latch connected to the respective enable input of one the plurality of output stages to provide its enable signal to its respective output stage.
6 more elements
A method for adjusting a strength of an output buffer, comprising:
- generating enable signals for a plurality of parallel output buffer stages;
- enabling each stage having an enable signal;
- and
- combining the strength of each enabled stage into a total buffer strength;
- wherein generating enable signals comprises:
- programming a bank of trim latches with a plurality of values representative of enable signals;
- and
- connecting an output of each trim latch to a respective output buffer stages.
5 more elements
A method of adjusting output buffer strength in a multiple stage output buffer, comprising:
- selecting predetermined non-volatile or programmable variable enable inputs for the output stages;
- programming the programmable variable enable inputs when programmable variable enable inputs are selected;
- and
- passing the predetermined non-volatile enable inputs when predetermined non-volatile enable inputs are selected.
1 more element
A method of operating an integrated circuit, comprising:
- programming a selectable input fuse to generate an active selectable input enable signal;
- programming a predetermined non-volatile enable signal set;
- programming a selectable variable input set;
- and
- selecting between the predetermined non-volatile enable set and the selectable variable input set.
2 more elements
Dependencies are inferred from the claim text.