US 7,064,579 B2 · Alterable application specific integrated circuit (ASIC)

Abstract

A highly economical alterable ASIC contains multiple fully optimized custom ASIC designs in one IC foot-print, each design utilizing the entire IC. The user can switch between multiple independently stored optimized logic applications instantly. The alterable ASIC comprises programmable logic blocks and user configurable circuits. Either random access memory (RAM) configuration circuits or mask configured read only memory (ROM) configuration circuits are stacked in separate module layers above a single logic module layer. Each RAM or ROM layer implements one design application and global control signals provide user selection. Alterable ASIC dissever the effective die cost, requires one smaller package, occupies one site on the PC board and needs less board level wires. An extremely low cost solution for system designs is realized with an alterable ASIC.

Claims20

Dependent claims

A three-dimensional semiconductor device, comprising:

a first module layer having a plurality of circuit blocks;
and
a second module layer positioned substantially above the first module layer, including a plurality of first configuration circuits to control a portion of the circuit blocks;
and
a third module layer positioned substantially above the first module layer, including a plurality of second configuration circuits to control said portion of the circuit blocks;
and
a first global control signal to couple or decouple each of said first configuration circuits from said portion of circuit blocks, and
a second global control signal to couple or decouple each of said second configuration circuits from said portion of circuit blocks;
wherein said global control signals instantly select all configuration circuits in one of said modules to control said portion of the circuit blocks.

6 more elements

A programmable storage unit in an integrated circuit that generates an output coupled to a high impedance device, said storage unit comprising:

a first select device coupled to said output;
and
a first configuration memory circuit coupled to said first select device;
and
a first control signal coupled to said first select device to selectively couple or decouple said first configuration memory circuit from said output;
and
a second select device coupled to said output;
and
a second configuration memory circuit coupled to said second select device;
and
a second control signal coupled to said second select device to selectively couple or decouple said second configuration memory circuit from said output;
wherein, the high impedance device is located in a first module layer, the first configuration memory circuit is located in a second module layer positioned above said first module layer, and the second configuration memory circuit is located in a third module layer positioned above said second module layer;
and
wherein, the output value can be switched between the first and second configuration memory bits instantly by activating said first or second control signal respectively.

11 more elements

An alterable application specific integrated circuit (ASIC) that can instantly switch between N independently stored logic applications, wherein N is an integer value greater than one, the ASIC comprising:

a plurality of programmable N-bit storage units, each unit generating a single output that couples to a high impedance device, each storage unit comprised of:
a first storage state comprising:
a first select device coupled to said output;
and
a first configuration memory circuit coupled to said first select device;
and
a first control signal coupled to said first select device to selectively couple or decouple said first configuration memory circuit from said output;
and
a second storage state comprising:
a second select device coupled to said output;
and
a second configuration memory circuit coupled to said second select device;
and
a second control signal coupled to said second select device to selectively couple or decouple said second configuration memory circuit from said output;
and
additional (N−3) similar storage states;
and
an Nth storage state comprising:
an Nth select device coupled to said output;
and
an Nth configuration memory circuit coupled to said Nth select device;
and
an Nth control signal coupled to said Nth select device to selectively couple or decouple said Nth configuration memory circuit from said output;
and
a first global control signal, said signal comprised of coupling together the first control signal of every storage unit in the first storage state;
and
a second global control signal, said signal comprised of coupling together the second control signal of every storage unit in the second storage state;
and
additional (N−3) similar global control signals;
and
an Nth global control signal, said signal comprised of coupling together the Nth control signal of every storage unit in the Nth storage state;
wherein, the plurality of high impedance devices are located in a first module layer, the plurality of first configuration memory circuits are located in a second module layer positioned above said first module layer, and the plurality of second configuration memory circuits are located in a third module layer positioned above said second module layer, and so forth sequential positioning for additional (N−3) module layers, and the plurality of Nth configuration memory circuits are located in an Nth module layer positioned above the (N−1) module layer;
and
wherein, activating one of said first thru Nth global control signals enables instant switching between the N stored logic applications.

31 more elements

Dependencies are inferred from the claim text.

Alterable application specific integrated circuit (ASIC)

Life of this patent

Alterable application specific integrated circuit (ASIC)

Life of this patent

Abstract

Claims20