Distributed bus structure

A programmable logic device, comprising:

• a plurality of logic elements arranged in an array, the array comprising rows and columns of logic elements, the rows of said array being located at respective vertical positions in said array, and the columns of said array being located at respective horizontal positions in said array;
• and
• a routing structure, wherein the routing structure comprises a first plurality of routing lines, running parallel to said rows of logic elements at a first vertical position in said array;
• a second plurality of routing lines, running parallel to said rows of logic elements at a second vertical position in said array, a third plurality of routing lines, running parallel to said columns of logic elements at a first horizontal position in said array;
• and a fourth plurality of routing lines, running parallel to said columns of logic elements at a second horizontal position in said array,
• wherein each routing line comprises:
• a plurality of first OR gates, each first OR gate having at least a first input connected to a respective one of said logic elements in a respective first group of said logic elements, and each first OR gate except a final first OR gate in said line having an output connected to a second input of a respective succeeding one of said first OR gates, such that a signal from one of said logic elements in the first group of logic elements appears on an output of the final first OR gate in said line;
• and
• a return line, comprising a plurality of drivers connected in series, each of said drivers having a connection to a plurality of said logic elements in a respective second group of logic elements, such that the signal appearing on said output of the final first OR gate in said line may be passed to said plurality of logic elements in the second group of logic elements.

In a programmable logic device, comprising a plurality of logic elements and a routing structure, wherein the routing stricture comprises a plurality of distributed OR gates, each distributed OR gate comprising logic circuitry having a plurality of inputs from a first plurality of logic elements distributed amongst said logic elements and forming a logic OR function from said inputs, and an output of each distributed OR gate being connected to a second plurality of logic elements distributed amongst said logic elements, a method of forming a bus structure, the method comprising:

• allocating functionality to said first plurality of logic elements, and to said second plurality of logic elements in a first distributed OR gate;
• and
• controlling said first plurality of logic elements such that they each output a logical zero except when involved in a data transaction,
• such that outputs from said first plurality of logic elements are multiplexed together, and made available to said second plurality of logic elements via a return line coupled to an end OR gate of the plurality of distributed OR gates.