Method and apparatus for supporting variable speed configuration hardware
AssigneeAltera Corporation
InventorAndy L. Lee
Life of this patent
Estimating the term…
Abstract
A programmable logic device (PLD) includes a plurality of programmable resources. The PLD includes configuration hardware that configures a first programmable resource at a first rate and a second programmable resource at a second rate with data that is provided to the configuration hardware at the first rate.
Claims18
A method for formatting data for programming a programmable logic device (PLD), comprising:
- identifying a first type of data to be used for programming a first resource on the PLD at a first rate;
- identifying a second type of data to be used for programming a second resource on the PLD at a second rate;
- and
- generating additional copies of the second type of data such that when the data is transmitted to the PLD at the first rate it appears to the PLD as if the second type of data is changing at the second rate.
A programmable logic device (PLD), comprising:
- a plurality of programmable resources;
- and configuration hardware that configures a first programmable resource at a first rate and a second programmable resource at a second rate with data that is provided to the configuration hardware, wherein the first rate is faster than the second rate.
A method for processing data for programming a programmable logic device (PLD), comprising:
- identifying a type of data received by determining whether the data received is header data, configuration shift register (CSR) data, or configuration random access memory (CRAM) data;
- adjusting a rate the data is latched in response to the type of data;
- and
- programming the PLD with the data at the rate.
A method for processing data for programming a programmable logic device (PLD), comprising:
- identifying a type of data received;
- adjusting a rate the data is latched in response to the type of data by selecting one of a first and second clock frequency in response to the type of data received, and toggling a data input register with the clock frequency selected;
- and
- programming the PLD with the data at the rate.
A method for processing data for programming a programmable logic device (PLD), comprising:
- identifying a type of data received;
- adjusting a rate the data is latched in response to the type of data;
- programming the PLD with the data at the rate;
- identifying a type of a second data received;
- adjusting a rate in which the second data is latched in response to the type of the second data;
- and
- programming the PLD with the second data at the rate in which the second data is latched.
A method for programming a programmable logic device (PLD), comprising:
- identifying a first type of data to be used for programming a first resource on the PLD at a first rate;
- identifying a second type of data to be used for programming a second resource on the PLD at a second rate;
- generating additional copies of the second type of data;
- transmitting data including the first type of data, the second type of data and the additional copies of the second type of data to the PLD at the first rate;
- identifying a type of data received at the PLD;
- adjusting a rate the data is latched in response to the type of data;
- and
- programming a resource on the PLD with the data at the rate.
Dependencies are inferred from the claim text.