Techniques for reducing leakage current in on-chip impedance termination circuits
AssigneeAltera Corporation
InventorSimar Maangat
Life of this patent
Estimating the term…
Abstract
Techniques for reducing the leakage currents through on-chip impedance termination circuits are provided. An on-chip impedance termination circuit includes a network of resistors and transistors formed on an integrated circuit. The termination circuit is coupled to one or more IO pins. The transistors can be turned ON and OFF to couple or decouple subsets of the resistors from the IO pins. The bodies of transistors 305–306 are coupled to a supply voltage to cut off leakage current. By pulling the body of these transistors to a supply voltage, the transistor's drain/source-to-body diodes turn OFF preventing unwanted leakage current. Also, by moving the source/drain/body node of transistors 301–304 to Node 2, leakage currents through transistors 301–304 are eliminated.
Claims35
An integrated circuit comprising a first impedance termination circuit, the first impedance termination circuit comprising:
- a first termination impedance coupled in series with a first pin of the integrated circuit;
- and
- a first transistor coupled in series with the first termination impedance, the first transistor having a body, a first current-carrying terminal coupled to the first termination impedance, a second current-carrying terminal, and an enable terminal, wherein when the enable terminal is biased to turn the first transistor OFF, the body of the first transistor is biased to block current flow through the first termination impedance and the first pin.
An integrated circuit comprising:
- a first programmable resistor coupled in series between a first pin and a common node, wherein the first programmable resistor includes a first transistor having a body, wherein when the first transistor is biased OFF, the body of the first transistor is biased to block current flow through the first programmable resistor;
- and
- a second programmable resistor coupled in series between a second pin and the common node, wherein the second programmable resistor includes a second transistor having a body, wherein when the second transistor is biased OFF, the body of the second transistor is biased to block current flow through the second programmable resistor.
A method of operating a termination circuit comprising:
- providing a termination impedance in series with a field effect transistor and an input/output pin;
- and
- biasing a body of the field effect transistor to prevent current flow through the termination impedance and the input/output pin when the field effect transistor is biased to an OFF state.
Dependencies are inferred from the claim text.