PLD memory cells utilizing metal-to-metal capacitors to selectively reduce susceptibility to single event upsets

A method of reducing the susceptibility of a programmable logic device (PLD) to single event upsets (SEUs), the PLD comprising a configuration plane and a user plane, the configuration plane comprising configuration memory cells and the user plane comprising user storage elements controlled by the configuration memory cells, the method comprising:

• implementing the configuration memory cells to include a metal-to-metal capacitor on at least one storage node in each of the configuration memory cells, the metal-to-metal capacitors providing additional capacitance not included in an intrinsic capacitance of the configuration memory cells, wherein each metal-to-metal capacitor extends beyond a boundary of the corresponding configuration memory cell;
• and
• implementing the user storage elements while omitting the additional capacitance from storage nodes in each user storage element.

A method of reducing the susceptibility of a programmable logic device (PLD) to single event upsets (SEUs), the PLD comprising a configuration plane and a user plane, the configuration plane comprising configuration memory cells and the user plane comprising configurable user elements controlled by the configuration memory cells, the method comprising:

• implementing the configuration memory cells to include a metal-to-metal capacitor on at least one storage node in each of the configuration memory cells, the metal-to-metal capacitors providing additional capacitance not included in an intrinsic capacitance of the configuration memory cells, wherein each metal-to-metal capacitor extends beyond a boundary of the corresponding configuration memory cell;
• and
• coupling at least one of the configuration memory cells to each of the configurable user elements.