Multiple-select multiplexer circuit, semiconductor memory device including a multiplexer circuit and method of testing the semiconductor memory device

A multiplexer circuit comprising:

• a plurality of basic unit circuits each supplied with a data signal and a select signal, commonly supplied with a clock signal for controlling operation timing, and having an output terminal;
• a common line connected commonly to the output terminal of said plurality of basic unit circuits;
• and
• an output buffer connected to the common line, and outputting the signal of the common line, said plurality of basic unit circuits each including:
• an unmatch detection circuit detecting unmatch of the data signal with the signal of the common line;
• a drive timing control circuit supplied with an output signal of the unmatch detection circuit, the data signal and the select signal, and outputting the select signal and the select signal in accordance with the output signal of the unmatch detection circuit when the clock signal is in a non-active state while keeping an old output state when the clock signal is in an active state;
• and
• a tri-state buffer receiving an output signal of the drive timing control circuit, and driving the common line according to a state of the data signal when the clock signal is in an active state.

A semiconductor memory circuit device comprising:

• a plurality of memory segments each including:
• a memory cell array having matrix-like arrayed memory cells;
• a row decoder for selecting one row of the memory cell array;
• a segment select circuit outputting a segment select signal for selecting the row decoder in accordance with a first control signal and an address signal;
• a plurality of data lines outputting a plurality of-bit read data read from the row of the memory cell array selected by the row decoder;
• and
• a plurality of first basic unit circuits each having an output terminal, supplied with the segment select signal and a second control signal, and provided by the number corresponding to said plurality of data lines;
• a plurality of common lines connected commonly with the output terminals of several basic unit circuits of the corresponding column of said plurality of first basic unit circuits;
• and
• a plurality of output buffer s connected to said plurality of common lines, and outputting signals of said plurality of common lines,
• said plurality of first basic unit circuits each including:
• a first unmatch detection circuit detecting an unmatch state of each data signal with each signal of the common lines;
• a first drive timing control circuit supplied with an output signal of the first unmatch detection circuit, the data signal, the segment select signal and the second control signal, outputting the select signal and an output signal of the segment select circuit in accordance with the output signal of the first unmatch detection circuit when the second control signal is in a non-active state while keeping an old output state when the second control signal is in an active state;
• and
• a first tri-state buffer receiving an output signal of the first drive timing generator circuit, driving each of said plurality of common lines according to a state of the data signal in synchronous with the second control signal, and keeping a state for an active period of the second control signal while the output becomes high impedance state when the second control signal becomes a non-active state;
• in a normal operation, memory cells included in one row of one memory segment being selected by the combination of the segment select signal and the address signal, and data signals read from memory cells equivalent to one row being each outputted to the corresponding common lines via the corresponding first basic unit circuits,
• in a burn-in operation in a state after the device is packaged, a plurality of segment signals being simultaneously activated regardless of a state of the address signal, and a plurality of data signals read from memory cells included in all memory segments being read in parallel to said plurality of common lines via said plurality of first basic unit circuits.

A method of testing a semiconductor memory circuit device including,

• a plurality of memory segments each including,
• a memory cell array having matrix-like arrayed memory cells;
• a row decoder for selecting one row of the memory cell array;
• a segment select circuit outputting a segment select signal for selecting the row decoder in accordance with a first control signal and an address signal;
• a plurality of data lines outputting a plurality of-bit read data read from the row of the memory cell array selected by the row decoder;
• and
• a plurality of first basic unit circuits each having an output terminal, supplied with the segment select signal and a second control signal, and provided by the number corresponding to said plurality of data lines;
• a plurality of common lines connected commonly with the output terminals of several basic unit circuits of the corresponding column of said plurality of first basic unit circuits;
• a plurality of output buffer s connected to said plurality of common lines, and outputting signals of said plurality of common lines;
• and
• a plurality of second basic unit circuits for writing expected values, provided commonly with respect to said plurality of memory segments, having output terminals connected to said plurality of common lines, and supplied with a read expected value data signal and a third control signal for writing expected values,
• the method comprising:
• simultaneously selecting said plurality of memory segments, temporarily activating the third control signal after setting the read expected data signal, and setting data of the common lines by the second basic unit circuits in accordance with the read expected data signal;
• selecting several memory cells included in said plurality of memory segments according to the address signal, and inputting data signals read from said plurality of memory cells to the corresponding first basic unit circuits;
• and
• carrying out a parallel test with respect to memory cells included in said plurality of memory segments according to a state transition such that the output signal of the output buffer is unchanged if all data read from said plurality of memory cells are identical to data preset in the common line while the output signal becomes an inverted state if only one different data exists.