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US 7,064,531 B1Granted
PWM buck regulator with LDO standby mode
AssigneeMicrel, Inc.
InventorRaymond Zinn
Life of this patent
Estimating the term…
Abstract
A voltage regulator is disclosed having a PWM portion and an LDO portion on a single chip. The PWM portion switches a large MOS transistor (or synchronous MOS transistors) at a high frequency to supply medium and high currents (e.g., 600 mA) to a load. During a standby mode, the regulator switches to an LDO mode and disables the PWM portion. The LDO mode controls a very small MOS series transistor to supply the standby mode current. Since the gate of the series MOS transistor is small, only a small variation in gate charge is needed to adequately control the conductance of the series transistor during the standby mode. Therefore, much less control current is used by the LDO than if the LDO used a series transistor of the same size as the switching transistor.
Claims17
A voltage converter comprising:
- a pulse width modulation (PWM) regulator portion having a PWM control and at least one MOS switching transistor of a first size having a first terminal connected to an input voltage and a second terminal providing an output current to a load, the PWM control receiving a feedback voltage corresponding to an output voltage of the converter and switching the at least one MOS switching transistor at a duty cycle to maintain a regulated output voltage of the converter, the at least one MOS switching transistor of a first size providing up to a first maximum current to the load;
- a low dropout (LDO) regulator portion having an error amplifier and an MOS series transistor whose conductance is controlled by an output of the error amplifier, the error amplifier receiving a feedback voltage corresponding to an output voltage of the converter and generating an error signal based on a difference between the feedback voltage and a reference voltage, the MOS series transistor having a first terminal connected to an input voltage and a second terminal providing a regulated voltage to the load, the MOS series transistor being of a second size less than one-fifth the first size, the MOS series transistor providing up to a second maximum current to the load, the second maximum current being less than one-fifth the first maximum current;
- and
- a mode select circuit that receives a mode select signal in a first state indicating the onset of a low current mode and, in response, disables the PWM regulator portion and enables the LDO regulator portion, wherein the mode select circuit also receives a mode select signal in a second state indicating a non-low current mode and, in response, enables the PWM regulator portion and disables the LDO regulator portion,
- the PWM regulator portion, the LDO regulator portion, and the mode select circuit being formed on a single chip.
2 more elements
A method for voltage conversion comprising comprising:
- switching at least one MOS switching transistor of a first size at a duty cycle to maintain a regulated output voltage of a converter, the at least one MOS switching transistor providing up to a first maximum current to the load, the switching being controlled by a pulse width modulation (PWM) regulator portion having a PWM control, the at least one MOS switching transistor having a first terminal connected to an input voltage and a second terminal providing an output current to a load;
- receiving a feedback voltage by the PWM control corresponding to an output voltage of the converter to control the duty cycle of the at least one MOS switching transistor;
- controlling a conductance of an MOS series transistor by an output of an error amplifier in a low dropout (LDO) regulator portion of the converter, the MOS series transistor having a first terminal connected to an input voltage and a second terminal providing a regulated voltage to the load, the MOS series transistor being of a second size less than one-fifth the first size, the MOS series transistor providing up to a second maximum current to the load, the second maximum current being less than one-fifth the first maximum current;
- receiving a feedback voltage by the error amplifier corresponding to an output voltage of the converter and generating an error signal based on a difference between the feedback voltage and a reference voltage;
- receiving by a mode select circuit a mode select signal in a first state indicating the onset of a low current mode and, in response, disabling the PWM regulator portion and enabling the LDO regulator portion;
- and
- receiving by the mode select circuit a mode select signal in a second state indicating a non-low current mode and, in response, enabling the PWM regulator portion and disabling the LDO regulator portion,
- the PWM regulator portion, the LDO regulator portion, and the mode select circuit being formed on a single chip.
5 more elements
Dependencies are inferred from the claim text.