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US 7,064,453 B2Granted
Semiconductor memory device including a gate electrode with a recess
AssigneeSeiko Epson Corporation
InventorTetsumasa Sato
Life of this patent
Estimating the term…
Abstract
A configuration is provided to reduce variations in the width of the gate of a read-out transistor without increasing the surface area of a memory cell. To do this, a recess is provided in an inner corner of a gate electrode that is bent into an L-shape. The recess is located so as to face a rectangular portion of an active region of the memory cell.
Claims7
A semiconductor memory device, comprising:
- a first driver transistor having a gate and a drain;
- a second driver transistor including:
- a drain connected to the gate of the first driver transistor;
- and
- a gate connected to the drain of the first driver transistor;
- a first load transistor connected in series to the first driver transistor, the gate of the first load transistor being an extension of the gate of the first driver transistor;
- a second load transistor connected in series to the second driver transistor, the gate of the second load transistor being an extension of the gate of the second driver transistor;
- a first transfer gate including:
- a source connected to the drain of the first driver transistor,
- a drain connected to a first bit line;
- and
- a gate connected to a word line;
- a second transfer gate including:
- a source connected to the drain of the second driver transistor;
- a drain connected to a second bit line;
- and
- a gate connected to the word line;
- a read-out transistor connected in series to the second load transistor, the gate of the read-out transistor being a bended extension of the gate of the second load transistor, the gate of the second load transistor being L-shaped;
- and
- a recess provided in an inner corner of the gate of the second driver transistor, the second load transistor and the read-out transistor.
17 more elements
A semiconductor memory device, comprising:
- a first active region and a second active region separated from each other by an isolation region;
- a first gate electrode positioned so as to intersect the first active region at two places and used for a pair of transfer gates;
- a second gate electrode positioned so as to cut across the first active region and the second active region and used for a first driver transistor and a first load transistor;
- a third gate electrode bent and positioned so as to cut across the first active region as well as to cut across the second active region at two places, and used for a second driver transistor, a second load transistor, and a read-out transistor;
- and
- a recess provided in an inner corner of the third gate electrode.
3 more elements
A semiconductor memory device, comprising:
- a first active region having a U-shaped pattern;
- a second active region having a T-shaped pattern;
- an isolation region separating the first and the second active region from each other;
- a first gate electrode positioned so as to intersect the U-shaped pattern at two places and used for a pair of transfer gates;
- a second gate electrode positioned so as to cut across the U-shaped pattern and the T-shaped pattern and used for a first driver transistor and a first load transistor;
- a third gate electrode bent and positioned so as to cut across the U-shaped pattern as well as to cut across the T-shaped pattern at two places, and used for a second driver transistor, a second load transistor, and a read-out transistor;
- and
- a recess provided in an inner corner of the third gate electrode.
5 more elements
Dependencies are inferred from the claim text.