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US 7,064,451 B2Granted
Area array semiconductor device and electronic circuit board utilizing the same
AssigneeCanon Kabushiki Kaisha
InventorsKunio Satomi, Yasushi Takeuchi
Life of this patent
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Abstract
An area array semiconductor device is constituted of a circuit wiring substrate having a circuit wiring and a semiconductor chip mounted on the circuit wiring substrate and electrically connected with the circuit wiring. A sealing layer composed of a sealing resin is formed such that the sealing layer has an angle of 30° to 60° with respect to a side of the circuit wiring substrate.
Claims14
An area array semiconductor device comprising:
- a circuit wiring substrate having a top face with a circuit wiring;
- a semiconductor chip having a top face and a bottom face, the bottom face being mounted on the circuit wiring substrate and at least the top face is electrically connected with the circuit wiring;
- and
- a sealing layer composed of a sealing resin positioned on the entire top face of the semiconductor chip and a portion of the top face of the wiring substrate;
- wherein a thickness of the sealing layer on the top face of the semiconductor is smaller than a thickness of the sealing layer on the portion of the top face of the wiring substrate;
- and
- wherein the sealing layer is formed such that a periphery of the sealing layer has an angle of 30° to 60° with respect to a corresponding side of the circuit wiring substrate.
4 more elements
An area array semiconductor device comprising:
- an insulating interposer having a circuit;
- an integrated circuit chip having a top surface and a bottom surface, wherein the bottom surface of the chip is mounted on a top surface of the insulating interposer and at least the top surface of the chip is electrically connected to the circuit of the interposer, the chip having a plurality of sides, each of the sides being at an angle of 30° to 60° with respect to a corresponding side of the interposer;
- a resin provided on the entire top surface of the chip and a portion of the top surface of the insulating interposer,
- wherein a thickness of the resin on the top surface of the chip is smaller than a thickness of the rosin on the portion of the top surface of the insulating interposer;
- and
- wherein the resin has an outer boundary of a plurality of sides angled at the same angle with respect to the interposer as the integrated circuit chip.
3 more elements
An electronic circuit board comprising:
- a printed wiring board;
- an insulating interposer defining an upper and a lower surface, the interposer having a plurality of connecting lands and a plurality of solder balls providing electrical connection to the wiring board;
- the interposer also having a circuit;
- an integrated circuit chip having an upper surface and a lower surface, wherein the lower surface of the chip is in contact with the upper surface of the interposer and at least the upper surface is electrically connected to the circuit of the interposer, and the chip has a plurality of sides, each of the sides being at an angle of 30° to 60° with respect to a corresponding side of the interposer;
- a protective material provided on the entire upper surface of the chip and a portion of the upper surface of the insulating interposer, which is adapted, in conjunction with the insulating interposer, to provide protection from contamination and moisture in the atmosphere, and the material having an outer boundary of a plurality of sides angled at the same angle with respect to the interposer as the integrated circuit chip,
- wherein a thickness of die protective material on the top face of the chip is smaller than a thickness of the resin on the portion of the top surface of the insulating interposer.
3 more elements
Dependencies are inferred from the claim text.