US 7,064,432 B2Granted

Method and system for bonding a semiconductor chip onto a carrier using micro-pins

AssigneeThe Research Foundation of State University of New York

InventorsSangmin Lee, Michael Gurvitch, Serge Luryi

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Abstract

An anisotropically conductive layer “ACL” (50) for mechanical and electrical bonding of two circuit containing structures, such as a flip chip and carrier is disclosed. The ACL is formed of a rigid insulating substrate (72) or membrane (61) with a top and bottom planar surfaces formed with a plurality of pins therein. The pins extend beyond the top and bottom surfaces so that a portion of each pin is exposed. The pins provide electrical connection between contact terminals or pads of the flip chip and carrier and additionally provide mechanical support between the flip chip and carrier so that the flip chip can under go post-bonding processing without substantial deformation or breaking. A method of electrically and mechanically bonding the flip chip and carrier and a method of making a semiconductor device using the ACL is also disclosed.

Claims16

Dependent claims

A bonding interface for mechanical and electrical bonding of a first electronic device containing structure, having a respective bonding surface with at least one conductive first contact pad adjacent thereto, to a second electronic device containing structure having a respective bonding surface with at least one conductive second contact pad adjacent thereto, the first and second structures being arranged so that the respective bonding surfaces of the first and second structures are in opposing relationship to one another, comprising:

(a) a rigid insulating substrate having a first and a second planar surface, said first planar surface being parallel to said second planar surface;
and
(b) a multiplicity of rigid electrically conductive pins embedded in said insulating substrate wherein:
said multiplicity of pins are aligned substantially normal to said first and second planar surfaces of the substrate,
at least substantially all of said multiplicity of pins protrude from said first and second planar surfaces of the substrate,
said multiplicity of pins are spaced apart from one another,
at least substantially all of said multiplicity of pins are each separated from a nearest other one of said multiplicity of pins by no more than about 2 microns,
said multiplicity of pins are distributed throughout said insulating substrate so that said insulating substrate and the embedded multiplicity of pins bonds said first and second device containing structures by being interposed between the respective bonding surfaces of the structures so that the respective bonding surfaces are at respective ends of the at least substantially all of the multiplicity of pins, each one of the at least one first contact pad overlapping a particular one of the at least one second contact pad is electrically connected to said particular one of the at least one second contact pad by a respective group of a plurality of said at least substantially all of the multiplicity of pins, each pin of the respective group having respective ends thereof electrically and mechanically bonded to the electrically connected ones of the at least one first contact pad and the at least one second contact pad, and
said multiplicity of pins providing mechanical support to the respective bonding surfaces of the first and second device containing structures without the use of an adhesive.

6 more elements

A method for electrically and mechanically bonding a first electronic device containing structure having a first bonding surface with at least one conductive first contact pad adjacent thereto to a second electronic device containing structure having a second bonding surface with at least one conductive second contact pad adjacent thereto, the first and second structures being arranged so that the respective bonding surfaces of the first and second structures are in opposing relationship to one another, comprising:

(a) providing a rigid insulating substrate with a first and second planar surface, said first planar surface being parallel to said second planar surface;
(b) embedding a multiplicity of rigid electrically conductive pins in said insulating substrate aligned substantially normal to said first and second planar surfaces, wherein at least substantially all of said multiplicity of pins protrude from said first and second planar surfaces, said multiplicity of pins being spaced apart from one another and wherein at least substantially all of said multiplicity of pins are each separated from a nearest other one of said multiplicity of pins by no more than about 2 microns;
and
(c) bonding said first and second electronic device containing structures without the use of an adhesive by mechanically and electrically bonding to respective ones of the at least one first contact pad and the at least one second contact pad respective ends of each one of the multiplicity of pins extending from each one of the at least one first contact pad to a particular one of the at least one second contact pad.

1 more element

A method of making a semiconductor device, the method comprising:

(a) providing a semiconductor substrate having a plurality of layers formed on a first surface thereof,
(b) forming at least one first electrical contact pad on at least one of said layers;
(c) providing an electronic circuit containing carrier having an interface surface with at least one second electrical contact pad adjacent thereto;
(d) providing a rigid insulating substrate with a first and a second planar surface, said first planar surface being parallel to said second planar surface;
and
(e) embedding a multiplicity of rigid electrically conductive pins in said insulating substrate aligned substantially normal to said first and second planar surfaces, each of said multiplicity of pins having a first and second end, wherein at least substantially all of said multiplicity of pins protrude from said first and second planar surfaces by respective fixed amounts, said multiplicity of pins being spaced apart from one another, and each one of at least substantially all of said multiplicity of pins being separated from a nearest other one of said multiplicity of pins by no more than about 2 microns;
(f) arranging the semiconductor substrate, the electronic circuit containing carrier, the insulating substrate and the embedded multiplicity of pins so that the at least one first electrical contact pad and the interface surface are in opposing relationship to one another, and the insulating substrate and embedded multiplicity of pins are disposed therebetween;
(g) bonding the at least one first electrical contact pad on the at least one of said layers to the first ends of a respective first group of the multiplicity of pins without the use of an adhesive;
(h) electrically and mechanically bonding the at least one second electrical contact pad to the second ends of a respective second group of the multiplicity of pins without the use of an adhesive, each respective first group of the multiplicity of pins having at least a plurality of pins in common with each respective second group of the multiplicity of pins so as to electrically connect each one of the at least one first electrical contact pad with a respective one of the at least one second electrical contact pad;
(i) after said bonding steps (g) and (h), carrying out a at least one processing step on a second surface of said semiconductor substrate having the plurality of layers formed thereon;
and
(j) forming at least one third electrical contact pad adjacent to said second surface of said semiconductor substrate facing away from said multiplicity of pins.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/333,199Filed 26 Jul 2001 · us provisional application
Priority: 26 Jul 2000
Published: US 2004/0038496 A126 Feb 2004
Granted: 20 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H05K 3/325
Electrically connecting electric components or wires to printed circuits: by abutting or pinching; Mechanical auxiliary parts therefor
H10W 70/095
Of insulating or insulated package substrates, or of interposers, or of redistribution layers: of vias therein
H10W 70/635
Vias, e.g. via plugs: through-vias
H05K 3/3436
Leadless components: having an array of bottom contacts, e.g. pad grid array or ball grid array components