Die attach region for use in a micro-array integrated circuit package
AssigneeNational Semiconductor Corporation
InventorsJaime A. Bayan, Ashok S. Prabhu, Chan Chee Ling, Lye Meng Kong, Santhiran S O Nadarajah
Life of this patent
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Abstract
A die attach region for use in an IC package is described. The die attach region employs a number of posts interconnected with a number of support risers to provide a structure that upholds a semiconductor die while facilitating flow of an encapsulant material underneath the die during encapsulation. The posts and risers can be arranged in a number of configurations that each facilitate flow of encapsulant material. This die attach region can be incorporated into a lead-frame structure or a substrate panel for ease and efficiency of manufacture.
Claims19
A micro-array lead-frame comprising:
- a plurality of leads, each lead including an elongated lead trace portion and a lead contact post, the lead contact posts being exposed at a bottom surface of the lead-frame and the lead trace portions not being exposed at the bottom surface of the lead-frame, wherein the lead trace portions of at least some of the leads have segments extending between lead contact posts associated with adjacent leads;
- and
- a die attach structure configured to support a semiconductor die, the die attach structure including a plurality of electrically connected support risers and a plurality of die attach posts that are integrally formed with the support risers, the support risers being configured to support a semiconductor die and to carry the die attach posts, wherein the die attach posts are exposed at the bottom surface of the lead-frame and the support risers are not exposed at the bottom surface of the lead-frame.
A micro-array lead-frame for use in an integrated circuit package, comprising:
- a plurality of leads configured for electrical connection to a semiconductor die;
- and
- a lattice structure configured to support a semiconductor die, the lattice structure having:
- a plurality of posts, each post having an upper surface configured for attachment to a semiconductor die, and a lower surface configured for attachment to a solder bump;
- and
- a plurality of partially etched struts interconnecting the posts, the struts maintaining distances between the posts so as to facilitate the flow of an encapsulant material therebetween.
A substrate panel for use in the packaging of integrated circuits, comprising:
- a lead-frame panel including an array of device areas, each device area having a plurality of conductive leads and a die attach structure, the die attach structure including a plurality of electrically connected support risers and a plurality of die attach posts that are integrally formed with the support risers, the support risers being configured to support a semiconductor die and to carry the die attach post, wherein the die attach posts are exposed at the bottom surface of the lead-frame and the support risers are not exposed at the bottom surface of the lead-frame.
Dependencies are inferred from the claim text.