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US 7,064,398 B2Granted
Semiconductor memory device
AssigneeRenesas Technology Corp.
InventorTakahiro Yokoyama
Life of this patent
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Abstract
In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistors, first and second load MOS transistors and first and second access MOS transistors, two capacitors are arranged spaced apart from each other on embedded interconnections to be storage nodes, with lower and upper cell plates cross-coupled to each other.
Claims9
A semiconductor memory device, comprising:
- a word line;
- a bit line extending in a direction orthogonal to an extending direction of said word line;
- and
- a memory cell longer in the extending direction of said word line than in an extending direction of said bit line;
- said memory cell including
- a first well region of a first conductivity type, a second well region of a second conductivity type and a third well region of the first conductivity type arranged side by side in the extending direction of said word line,
- a first driver MOS transistor and a first access MOS transistor formed on said first well region,
- first and second load MOS transistors formed on said second well region,
- a second driver MOS transistor and a second access MOS transistor formed on said third well region,
- a first local interconnection formed in an interlayer insulating film covering said first and second driver MOS transistors, said first and second access MOS transistors and said first and second load MOS transistors, and connecting active regions of said first driver MOS transistor, said first access MOS transistor and said first load MOS transistor with gate electrodes of said second driver MOS transistor and said second load MOS transistor,
- a second local interconnection formed in said interlayer insulating film, and connecting active regions of said second driver MOS transistor, said second access MOS transistor and said second load MOS transistor with gate electrodes of said first driver MOS transistor and said first load MOS transistor,
- first and second lower plates formed spaced apart from each other on said interlayer insulating film, and
- first and second upper plates formed on said first and second lower plates, respectively, with dielectric films interposed therebetween, and forming first and second capacitors together with said first and second lower plates, respectively,
- wherein said second upper plate and said first lower plate, and said first upper plate and said second lower plate are connected via first and second contact holes, respectively, formed in said dielectric films, the first and second contact holes being formed on the first and second local interconnections, respectively.
11 more elements
A semiconductor memory device, comprising:
- a memory cell having a first driver MOS transistor and a first access MOS transistor formed in a first well region of a first conductivity type, first and second load MOS transistors formed in a second well region of a second conductivity type, and a second driver MOS transistor and a second access MOS transistor formed in a third well region of the first conductivity type,
- said memory cell including
- a first local interconnection formed in an interlayer insulating film covering said first and second driver MOS transistors, said first and second access MOS transistors and said first and second load MOS transistors, and connecting active regions of said first driver MOS transistor, said first access MOS transistor and said first load MOS transistor with gate electrodes of said second driver MOS transistor and said second load MOS transistor,
- a second local interconnection formed in said interlayer insulating film, and connecting active regions of said second driver MOS transistor, said second access MOS transistor and said second load MOS transistor with gate electrodes of said first driver MOS transistor and said first load MOS transistor,
- a first capacitor provided on said interlayer insulating film and connected to said first and second local interconnections, and
- a second capacitor provided on said interlayer insulating film and connected to said second and first local interconnections,
- the semiconductor memory device further comprising a word line, a bit line, a ground line and a power supply line in a layer upper than that of said first and second capacitors.
4 more elements
Dependencies are inferred from the claim text.