US 7,064,395 B2Granted

Semiconductor device and method for fabricating the same

AssigneeFujitsu Limited

InventorsTakayoshi Minami, Yuji Setta

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Abstract

The semiconductor device comprises a gate interconnection 24a including a gate electrode formed over a semiconductor substrate 14 with a gate insulation film 22 formed therebetween; a first source/drain diffused layer 28 formed near the end of the gate interconnection 24a; a second source/drain diffused layer 34 formed remote from the gate interconnection 24a and the first source/drain diffused layer 28; and an insulation film 40 formed over the gate interconnection 24a, the first source/drain diffused layer 28 and the second source/drain diffused layer 34, and having a groove-shaped opening 42a formed in, which integrally exposes the gate interconnection 24a, one of the first source/drain diffused layer 28, and one of the second source/drain diffused layer 34; and a contact layer 48a buried in the groove-shaped opening 42a. The groove-shaped openings 42a for the contact layers 48a to be buried in can be formed without failure. Accordingly, it is possible to provide a semiconductor device which can realize the micronization without reliability decrease and fabrication yield decrease.

Claims22

Dependent claims

A semiconductor device comprising a memory cell including a first inverter including a first load transistor and a first driver transistor;

and a second inverter including a second load transistor and a second driver transistor, the semiconductor device further comprising:
a first gate interconnection formed over a semiconductor substrate and including a gate electrode of the first load transistor and a gate electrode of the first driver transistor;
an insulation film formed over the first gate interconnection and having a first groove-shaped opening formed in the first groove-shaped opening integrally exposing the first gate interconnection, one of source/drain diffused layer of the second load transistor and one of source/drain diffused layer of the second driver transistor;
and
a first contact layer buried in the first groove-shaped opening,
wherein the semiconductor device further comprises a second gate interconnection formed over the semiconductor substrate and including a gate electrode of the second load transistor and a gate electrode of the second driver transistor, and
a second groove-shaped opening is formed in the insulation film, the second groove-shaped opening integrally exposing the second gate interconnection, one of source/drain diffused layer of the first load transistor and one of source/drain diffused layer of the first driver transistor, and
a second contact layer is buried in the second groove-shaped opening.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/788,379Filed 1 Mar 2004
Priority: JP 2003-29867822 Aug 2003
Published: US 2005/0040468 A124 Feb 2005
Granted: 20 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10B 10/00
Static random access memory [sram] devices
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes