Metal gate engineering for surface p-channel devices
AssigneeMicron Technology, Inc.
InventorYongjun Jeff Hu
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Abstract
A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.
Claims8
Complimentary semiconductor devices comprising:
- a semiconductive substrate;
- complimentary NMOS and PMOS doped regions formed in the substrate;
- a dielectric layer positioned on the semiconductive substrate;
- and
- an interconnecting layer positioned on the dielectric layer wherein the interconnecting layer comprises a metal silicide having a first work function wherein the metal of the metal silicide is matched with the silicide such that the metal is inhibited from reacting with the dielectric layer and wherein the interconnecting layer overlying the NMOS regions comprises the metal silicide being further nitrided so as to have a second lower work function.
Dependencies are inferred from the claim text.