Back to results
US 7,064,389 B2Granted
Semiconductor memory device having full depletive type logic transistors and partial depletion type memory transistors
AssigneeOki Electric Industry Co., Ltd.
InventorMasahiro Yoshida
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a semiconductor substrate, an insulating layer, a silicon layer, full depletion type transistors, and partial depletion type transistors. The insulating layer is formed on the semiconductor substrate. The silicon layer has a first region and a second region. The silicon layer is formed on the insulating layer. The full depletion type transistors are used for a logical circuit, and are formed on the silicon layer at the first region. The partial depletion type transistors are used for a memory cell circuit and are formed on the silicon layer at the second region. The second region of the silicon layer is maintained at a fixed potential.
Claims20
A semiconductor device comprising:
- a semiconductor substrate;
- an insulating layer formed on the semiconductor substrate;
- a silicon layer formed on the insulating layer, the silicon layer having a first region and a second region, the first region of the silicon layer having a plurality of first element regions and the second region of the silicon layer having a plurality of second element regions;
- an element isolation layer formed on the silicon layer, the element isolation layer completely isolating the first element regions from each other and isolating the second element regions from each other only at a surface of the second region of the silicon layer, the element isolation layer additionally isolating the first region of the silicon layer from the second region of the silicon layer;
- a plurality of full depletion type transistors used for a first circuit each formed on the silicon layer at the first region;
- and
- a plurality of partial depletion type transistors used for a second circuit each formed on the silicon layer at the second region, the silicon layer in the second region being applied with a predetermined potential.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate;
- an insulating layer formed on the semiconductor substrate;
- a first silicon layer and a second silicon layer formed on the insulating layer, the first silicon layer having a plurality of first element regions and the second silicon layer having a plurality of second element regions;
- an element isolation layer formed on the first and second silicon layers, the element isolation layer completely isolating the first element regions from each other and isolating the second element regions from each other only at a surface of the second silicon layer;
- a plurality of full depletion type transistors used for a first circuit formed on the first silicon layer;
- and
- a plurality of partial depletion type transistors used for a second circuit formed on the second silicon layer, wherein the second silicon layer is fixed at a fixed potential.
4 more elements
A semiconductor device comprising:
- a semiconductor substrate having an insulating layer formed thereon, the semiconductor substrate having a first area and a second area;
- a silicon layer formed on the insulating layer, the silicon layer having a plurality of first element regions above the first area of the substrate and a plurality of second element regions above the second area of the substrate;
- an element isolation layer formed on the silicon layer, the element isolation layer completely isolating the first element regions from each other and isolating the second element regions from each other only at a surface of the silicon layer, the element isolation region additionally isolating a portion of the silicon layer where the first element regions are disposed from a portion of the silicon layer where the second element regions are disposed;
- a plurality of fully depleted transistors formed on the silicon layer above the first area, the fully depleted transistors being used for a first circuit;
- a plurality of partially depleted transistors formed on the silicon layer above the second area, the partially depleted transistors being used for a second circuit;
- and
- a potential applying region formed on the silicon layer above the second area, the potential applying region having a high concentration area for applying a predetermined potential to the silicon layer,
- wherein the silicon layer of the potential applying region is connected to the silicon layer at which one of the partially depleted transistors is formed.
5 more elements
Dependencies are inferred from the claim text.