Ferroelectric memory devices having an expanded plate electrode

A ferroelectric memory device, comprising:

• a plurality of cell transistors arranged in a row and column relationship on an integrated circuit substrate;
• a bottom interlayer dielectric layer covering a surface of the integrated circuit substrate in a region including the plurality of cell transistors;
• ferroelectric capacitors arranged in a row and column relationship on the bottom interlayer dielectric layer in the region including the plurality of cell transistors, the ferroelectric capacitors being electrically connected to associated ones of the cell transistors through respective storage node contact holes penetrating the bottom interlayer dielectric layer;
• a top interlayer dielectric layer formed on the bottom interlayer dielectric layer including the ferroelectric capacitors, the top interlayer dielectric layer including a plurality of via holes disposed on the ferroelectric capacitors;
• a plurality of plate electrodes formed in the top interlayer dielectric layer and extending into respective ones of the via holes in the top interlayer dielectric layer to contact top surfaces of at least two neighboring ones of the ferroelectric;
• and
• a hydrogen barrier layer pattern interposed between the ferroelectric capacitors and the top interlayer dielectric layer and extending along sidewalls of the ferroelectric capacitors and an edge portion of the top surfaces of the ferroelectric capacitors, the via holes of the top interlayer dielectric layer extending through the hydrogen barrier layer to expose the top surfaces of the ferroelectric capacitors.