US 7,064,090 B2Granted

Method of manufacturing a semiconductor integrated circuit device

AssigneeHitachi, Ltd.

InventorsShinichi Minami, Yoshiaki Kamigaki, Hideki Yasuoka, Fukuo Owada

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Abstract

A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.

Claims24

Dependent claims

A method of manufacturing a semiconductor integrated circuit device comprising:

(a) forming a semiconductor region of a first conductivity type in a first region at a primary face of a semiconductor substrate of said first conductivity type, and then forming, on said semiconductor substrate above said semiconductor region of the first conductivity type, a semiconductor region of a second conductivity type having a greater area of a planar pattern than said semiconductor region of the first conductivity type such that there is formed a zener diode comprised of said semiconductor region of the first a conductivity type and said semiconductor region of the second conductivity type, wherein said semiconductor region of the second conductivity type, constituting a part of said zener diode, is formed simultaneously to the forming of another semiconductor region of the second conductivity type for producing a source and a drain of a MISFET formed in a second region at the primary face of said semiconductor substrate;
(b) forming an insulation film on the primary face of said semiconductor substrate, and then forming a plurality of connection holes in said insulation film which are extended to an upper part of a region located outside a junction formed between the semiconductor regions of said first and second conductivity types;
and
(c) forming a wire at the upper part of said insulation film, wherein said wire and said semiconductor region of said second conductivity type effect an electrical connection through said plurality of connection holes.

1 more element

A method of manufacturing a semiconductor integrated circuit device comprising:

(a) forming an element isolation portion in a semiconductor substrate of a first conductivity type, and forming a MISFET forming region and a diode forming region that are separated by said element isolation portion;
(b) forming a first semiconductor region of said first conductivity type in said diode forming region, said first semiconductor region having an impurity concentration higher than that of said semiconductor substrate;
(c) forming a gate electrode of a MISFET on said MISFET forming region;
and
(d) forming a second semiconductor region of a second conductivity type, opposite to said first conductivity type, in said MISFET forming region and in said diode forming region, wherein said second semiconductor region of said diode forming region is formed above said first semiconductor region and has a larger area, defined by a planar pattern thereof, than said first semiconductor region.

2 more elements

A method of manufacturing a semiconductor integrated circuit device comprising:

(a) forming an element isolation portion in a semiconductor substrate, and forming a MISFET forming region and a diode forming region that are separated by said element isolation portion;
(b) forming first wells in said MISFET forming region and said diode forming region, said first wells having a first conductivity type;
(c) forming a first semiconductor region of said first conductivity type in said diode forming region, said first semiconductor region having an impurity concentration higher than that of said first wells;
(d) forming a gate electrode of a MISFET on said MISFET forming region;
and
(e) forming second semiconductor regions of a second conductivity type, opposite to said first conductivity type, in said first wells, wherein, in said diode forming region, the planar size of said second semiconductor region is larger than that of said first semiconductor region, and the depth of said first semiconductor region is deeper than that of said second semiconductor region.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/942,860Filed 17 Sep 2004 · division
Priority: JP 2000-02092028 Jan 2000
Published: US 2005/0032298 A110 Feb 2005
Granted: 20 Jun 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/49
Simultaneous manufacture of periphery and memory cells: comprising different types of peripheral transistor
H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…

Family

Application09/768,471Parent of this division · filed 25 Jan 2001
US 2005/0032298 A1Pre-grant publication · published 10 Feb 2005
US 6,803,644 B2Parent of this division
US 2001/0013611 A1Published application
US 7,064,090 B2This patent

From the US filing history. Foreign family members aren’t listed.