Reduction of lateral silicide growth in integrated circuit technology
AssigneeAdvanced Micro Devices, Inc.
InventorsPaul L. King, Simon Siu-Sing Chan, Jeffrey P. Patton, Minh Van Ngo
Life of this patent
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Abstract
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.
Claims20
A method of forming an integrated circuit comprising:
- providing a semiconductor substrate;
- forming a gate dielectric on the semiconductor substrate;
- forming a gate on the gate dielectric;
- forming a sidewall spacer around the gate;
- forming source/drain junctions in the semiconductor substrate;
- forming an intermediate phase silicide on the source/drain junctions and on the gate;
- removing the sidewall spacer prior to forming a final phase silicide from the intermediate phase silicide;
- forming an interlayer dielectric above the semiconductor substrate;
- and
- forming contacts in the interlayer dielectric to the final phase silicide.
A method of reducing piping of a suicide formed over source/drain junctions in an integrated circuit having a gate comprising:
- forming a sidewall spacer around the gate;
- forming the source/drain junctions in the semiconductor substrate;
- forming an intermediate phase silicide on the source/drain junctions and on the gate;
- and
- removing the sidewall spacer prior to forming a final phase suicide from the intermediate phase silicide.
A method of reducing stress in the area of a semiconductor substrate around a gate comprising:
- forming a sidewall spacer around the gate;
- forming the source/drain junctions in the semiconductor substrate;
- forming an intermediate phase silicide on the source/drain junctions and on the gate;
- and
- removing the sidewall spacer prior to forming a final phase silicide from the intermediate phase silicide.
A method of forming a silicide in an integrated circuit having a spacer around a gate comprising:
- forming an intermediate phase silicide layer around the spacer;
- and removing the spacer prior to forming a final phase silicide form the intermediate phase silicide.
Dependencies are inferred from the claim text.