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US 7,064,058 B2Granted
Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics
AssigneeMicron Technology, Inc.
InventorsKie Y. Ahn, Leonard Forbes
Life of this patent
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Abstract
A praseodymium (Pr) gate oxide and method of fabricating same that produces a high-quality and ultra-thin equivalent oxide thickness as compared to conventional SiO2 gate oxides are provided. The Pr gate oxide is thermodynamically stable so that the oxide reacts minimally with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit a Pr layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
Claims65
A method comprising:
- thermal evaporation depositing a praseodymium (Pr) layer on a surface on a substrate;
- and
- oxidizing the Pr layer to form an oxide on the surface, the oxide including a praseodymium oxide layer, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides.
A method comprising:
- thermal evaporation depositing a praseodymium (Pr) layer on a surface on a substrate, the substrate having a substrate temperature ranging from about 150° C. to about 400° C.;
- and
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form an oxide on the surface, the oxide including a Pr2O3 layer, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides.
A method comprising:
- electron beam evaporation depositing a praseodymium (Pr) layer on a surface on a substrate, the substrate having a substrate temperature ranging from about 150° C. to about 400° C.;
- and
- oxidizing the Pr layer to form an oxide on the surface using an oxidation process that generates atomic oxygen or oxygen radicals without substantially generating molecular oxygen, the oxide including a praseodymium oxide layer, wherein electron beam evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides.
A method of forming a transistor, comprising:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- thermal evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide on the transistor body region, the gate oxide including a praseodymium oxide layer, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the gate oxide.
3 more elements
A method of forming a transistor, comprising:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- electron beam evaporation depositing a praseodymium (Pr) layer on the transistor body region, the substrate having a substrate temperature ranging from about 150° C. to about 400° C.;
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form a gate oxide on the transistor body region, the gate oxide including a Pr2O3 layer, wherein electron beam evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the gate oxide.
3 more elements
A method of forming a memory, comprising:
- forming a number of access transistors including:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- thermal evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide including a praseodymium oxide layer on the transistor body region, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the oxide layer;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- and
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
8 more elements
A method of forming a memory, comprising:
- forming a number of access transistors including:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- thermal evaporation depositing a praseodymium (Pr) layer on the transistor body region, the substrate having a substrate temperature ranging from about 150° C. to about 400° C.;
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form a gate oxide including a layer of Pr2O3 the transistor body region, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the oxide layer;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- and
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
8 more elements
A method of forming an information handling system, comprising:
- providing a processor;
- and
- coupling the processor to a memory using a system bus, the memory formed by a method including:
- forming a number of access transistors, including:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- thermal evaporation depositing a praseodymium (Pr) layer on the transistor body region;
- oxidizing the Pr layer to form a gate oxide including a praseodymium oxide layer on the transistor body region, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the gate oxide;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- and
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
11 more elements
A method of forming an information handling system, comprising:
- providing a processor;
- and
- coupling the processor to a memory using a system bus, the memory formed by a method including:
- forming a number of access transistors, including:
- forming first and second source/drain regions on a substrate;
- forming a transistor body region between the first and second source/drain regions;
- thermal evaporation depositing a praseodymium (Pr) layer on the transistor body region, the substrate having a substrate temperature ranging from about 150° C. to about 400° C.;
- oxidizing the Pr layer using a krypton (Kr)/oxygen (O2) mixed plasma process to form a gate oxide including a layer of Pr2O3 on the transistor body region, wherein thermal evaporation depositing the Pr layer and oxidizing the Pr layer are performed at substrate temperatures that inhibit formation of unwanted silicides and oxides;
- and
- coupling a gate to the gate oxide;
- forming a number of wordlines coupled to a number of the gates of the number of access transistors;
- forming a number of sourcelines coupled to a number of the first source/drain regions of the number of access transistors;
- and
- forming a number of bitlines coupled to a number of the second source/drain regions of the number of access transistors.
11 more elements
Dependencies are inferred from the claim text.