Method of fabricating semiconductor device

A method of fabricating a static random access memory (SRAM), comprising steps of:

• (a) forming a gate electrode of a n-channel MISFET over an element forming region of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over an element forming region of a second semiconductor region of n-type conductivity formed in said semiconductor body, wherein each of said element forming regions is defined by a shallow groove isolation layer such that said shallow groove isolation layer is formed by a CMP method;
• (b) after said step (a), implanting ions in said first semiconductor region to form a lightly doped drain;
• (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
• (d) after said step (c), implanting ions in a first region of said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
• (e) after said step (c), implanting ions in a second region, deeper than said first region, of said first semiconductor region to form a fifth semiconductor region of n-type conductivity;
• and
• (f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region,
• wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
• wherein said gate electrode of said n-channel MISFET is a N-type gate electrode, and
• wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.

A method of fabricating a static random access memory (SRAM), comprising steps of:

• (a) forming a gate electrode of a n-channel MISFET over an element forming region of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over an element forming region of a second semiconductor region of n-type conductivity formed in said semiconductor body;
• (b) after said step (a), implanting ions in said first semiconductor region to form a lightly doped drain;
• (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
• (d) after said step (c), implanting ions in a first region of said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
• (e) after said step (c), implanting ions in a second region, deeper than said first region, of said first semiconductor region to form a fifth semiconductor region of n-type conductivity;
• and
• (f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region,
• wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
• wherein said gate electrode of said n-channel MISFET is a N-type gate electrode, and
• wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.

A method of fabricating a static random access memory (SRAM), comprising steps of:

• (a) forming a gate electrode of a n-channel MISFET over an element forming region of a first semiconductor region of p-type conductivity formed in a semiconductor body and a gate electrode of a p-channel MISFET over an element forming region of a second semiconductor region of n-type conductivity formed in said semiconductor body, wherein a gate length of each of said gate electrodes is less than 200 nm;
• (b) after said step (a), implanting ions in said first semiconductor region to form a lightly doped drain;
• (c) after said step (b), forming side wall spacers on side surfaces of said gate electrodes;
• (d) after said step (c), implanting ions in a first region of said first semiconductor region to form a fourth semiconductor region of n-type conductivity;
• (e) after said step (c), implanting ions in a second region, deeper than said first region, of said first semiconductor region to form a fifth semiconductor region of n-type conductivity;
• and
• (f) after said steps (d) and (e), forming a cobalt silicide layer in said fourth semiconductor region,
• wherein a dose amount in said step (d) is greater than a dose amount in said step (e) such that an impurity concentration of said fourth semiconductor region is greater than an impurity concentration of said fifth semiconductor region,
• wherein said gate electrode of said n-channel MISFET is a N-type gate electrode, and
• wherein said gate electrode of said p-channel MISFET is a P-type gate electrode.