Technique for fabricating logic elements using multiple gate layers
AssigneeSanDisk Corporation
InventorsNima Mokhlesi, Jeffrey Lutze
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Abstract
Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and memory array cell sizes may be reduced by fabricating various transistor gates using multiple poly-silicon layers. The techniques of the present invention of using multiple layers of poly-silicon to form transistor gates of logic elements provides extra degrees of freedom in fine tuning transistor parameters such as, for example, oxide thickness, threshold voltage, maximum allowed gate voltage, etc.
Claims39
A method of forming a logic element of an integrated circuit, the logic element including a circuit portion configured or designed opexfonn at least one logic operation, the integrated circuit being fabricated on a substrate, the method comprising:
- forming a first gate over the substrate, the first gate being comprised La first transistor gate layer;
- forming a second gate over the substrate, the second gate being comprised of a second transistor gate layer;
- wherein a portion of the second gate is formed ova a first portion of the first gate, thereby forming a first overlapping gate region;
- forming a first electrical contact region on the first gate;
- forming a second electrical contact region on the second gate;
- wherein the first gate corresponds to a completed first transistor gate and wherein the second gate correspond to a completed second transistor gate of the circuit portion
- forming a first doped region in the substrate which functions as a source region of the circuit portion;
- forming a second doped region in the substrate which functions as a region of the circuit portion;
- forming an active region in the substrate between said source and regions, said active region being designed to enable current flow between said source and drain regions;
- wherein the first transistor gate includes an active region portion and a contact region portion, the active region portion corresponding to that portion of the first transistor gate which is over the active region:
- wherein the forming of the completed second transistor gate include removing portions of the second transistor gate layer in a manner which results in formation of the completed second transistor gate such that at least the portion of the completed second transistor gate is formed over the entirety of the active region portion of the first transistor gate;
- and
- forming the logic element in a manner which enables the logic element to perform at least one logic operation.
A method of forming a logic element of an integrated circuit, the integrated circuit being fabricated on a substrate, the integrated circuit including a circuit portion, the method comprising
- forming a first gate over the substrate, the first gate being comprised of a first transistor gate layer;
- forming a first dielectric layer between the first gate and the substrate such that the first gate is conductively isolated from the substrate;
- forming a second gate over the substrate, the second gate being comprised of a second transistor gate layer;
- forming a second dielectric layer between the second gate and the substrate such that the second gate is conductively isolated from the substrate;
- wherein a portion of the second gate is formed over a first portion of the first gate, thereby forming a first overlapping gate region;
- forming a first electrical contact region on the first gate;
- forming a second electrical contact region on the second gate;
- wherein the first gate corresponds to a first finalized transistor gate and wherein the second gate correspond to a second finalized transistor gate of the circuit portion;
- wherein the logic element corresponds to a transistor cell which includes the first finalized transistor gate and second finalized transistor gate;
- forming an active region in the substrate, said active region being designed to enable current flow between source and drain regions of the transistor cell;
- wherein the first finalized transistor gate includes an active region portion and a contact region portion, the active region portion corresponding to that portion of the first transistor gate which is over the active region;
- and
- removing portions of the second transistor gate layer to thereby form the second finalized transistor gate such that at least the portion of the second finalized transistor gate is formed over the entirety of the active region portion of the first finalized transistor gate.
Dependencies are inferred from the claim text.