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US 7,064,020 B2Granted
Method of manufacturing a semiconductor device having a gate electrode with a three layer structure
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei Yamazaki
Life of this patent
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Abstract
A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impurity region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.
Claims38
A method of fabricating a semiconductor device, comprising the steps of:
- forming a semiconductor layer over a substrate having an insulating surface;
- forming a gate insulating film in contact with said semiconductor layer;
- forming a first conductive layer;
- forming a second conductive layer on the first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said semiconductor layer with an impurity element of one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and an upper surface of said second layer of said gate electrode;
- etching said third conductive layer and said first conductive layer, thereby forming a third layer of said gate electrode and a first layer of said gate electrode;
- and
- doping a selected region of said semiconductor layer with an impurity element of said one conductivity type,
- wherein both edges of said first layer of said gate electrode are coplanar to those of said third layer of said gate electrode.
8 more elements
A method of fabricating a semiconductor device, comprising the steps of:
- forming a semiconductor layer over a substrate;
- forming a gate insulating film over said semiconductor layer;
- forming a first conductive layer over said gate insulating film;
- forming a second conductive layer directly on an upper surface of said first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said semiconductor layer with an impurity element of one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and on an upper surface of said second layer of said gate electrode;
- and
- etching said third conductive layer and said first conductive layer to form a third layer of said gate electrode and a first layer of said gate electrode.
6 more elements
A method of fabricating a semiconductor device, comprising:
- forming a first semiconductor layer and a second semiconductor layer over a substrate having an insulating surface;
- forming a gate insulating film on said first semiconductor layer and said second semiconductor layer;
- successively forming a first conductive layer and a second conductive layer on said gate insulating film wherein said second conductive layer is formed on the first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said first semiconductor layer with an impurity element of one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and on an upper surface of said second layer of said gate electrode;
- etching said third conductive layer and said first conductive layer to form a third layer of said gate electrode and a first layer of said gate electrode;
- doping a selected region of said first semiconductor layer and a selected region of said second semiconductor layer with an impurity element of said one conductivity type;
- and
- doping a selected region of said second semiconductor layer with an impurity of a conductivity type opposite to said one conductivity type,
- wherein both edges of said first layer of said gate electrode are coplanar to those of said third layer of said gate electrode.
8 more elements
A method of fabricating a semiconductor device, comprising the steps of:
- forming a first semiconductor layer and a second semiconductor layer over a substrate;
- forming a gate insulating film over said first semiconductor layer and said second semiconductor layer;
- forming a first conductive layer over said gate insulating film;
- forming a second conductive layer directly on an upper surface of said first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said first semiconductor layer with an impurity element of one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and on an upper surface of said second layer of said gate electrode;
- and
- etching said third conductive layer and said first conductive layer to form a third layer of said gate electrode and a first layer of said gate.
6 more elements
A method of fabricating a semiconductor device, comprising the steps of:
- forming a first semiconductor layer and a second semiconductor layer over a substrate having an insulating surface;
- forming a gate insulating film on said first semiconductor layer and said second semiconductor layer;
- successively forming a first conductive layer and a second conductive layer on said gate insulating film wherein said second conductive layer is formed on the first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said first semiconductor layer with an impurity element of one conductivity type;
- doping a selected region of said second semiconductor layer with an impurity of a conductivity type opposite to said one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and an upper surface of said second layer of said gate electrode;
- etching said third conductive layer and said first conductive layer to form a third layer of said gate electrode and a first layer of said gate electrode;
- and
- doping a selected region of said first semiconductor layer and a selected region of said second semiconductor layer with an impurity element of said one conductivity type,
- wherein both edges of said first layer of said gate electrode are coplanar to those of said third layer of said gate electrode.
8 more elements
A method of fabricating a semiconductor device, comprising the steps of:
- forming a first semiconductor layer and a second semiconductor layer over a substrate;
- forming a gate insulating film over said first semiconductor layer and said second semiconductor layer;
- forming a first conductive layer over said gate insulating film;
- forming a second conductive layer directly on an upper surface of said first conductive layer after forming said first conductive layer;
- etching said second conductive layer to form a second layer of a gate electrode;
- doping a selected region of said first semiconductor layer with an impurity element of one conductivity type;
- doping a selected region of said second semiconductor layer with an impurity of a conductivity type opposite to said one conductivity type;
- forming a third conductive layer on an upper surface of said first conductive layer and an upper surface of said second layer of said gate electrode;
- and
- etching said third conductive layer and said first conductive layer to form a third layer of said gate electrode and a first layer of said gate.
7 more elements
Dependencies are inferred from the claim text.