Method of making a semiconductor chip assembly with a pillar and a routing line using multiple etch steps

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and an etch mask on the second surface of the metal plate;
• then
• depositing a routing line on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the routing line contacts the first surface of the metal base and the etch mask contacts the second surface of the metal base;
• then
• mechanically attaching a semiconductor chip to the routing line, wherein the chip includes a conductive pad;
• electrically connecting the routing line to the pad;
• and
• etching the metal base using a first wet chemical etch that is selective of the metal plate with respect to the metal layer and the etch mask and then a second wet chemical etch that is selective of the metal layer and the etch mask, wherein an unetched portion of the metal base defined by the etch mask forms a pillar that contacts the routing line.

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and an etch mask on the second surface of the metal plate;
• then
• depositing a routing line on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the routing line contacts the first surface of the metal base and the etch mask contacts the second surface of the metal base;
• then
• mechanically attaching a semiconductor chip to the routing line, wherein the chip includes a conductive pad;
• electrically connecting the routing line to the pad;
• and
• etching the metal base using a first wet chemical etch and then a second wet chemical etch, wherein the first wet chemical etch is selective of the metal plate with respect to the metal layer and the etch mask and etches through the metal plate, thereby exposing the metal layer without exposing the routing line, and the second wet chemical etch is selective of the metal layer and the etch mask and etches through the metal layer, thereby exposing the routing line and removing the etch mask, and an unetched portion of the metal base defined by the etch mask forms a pillar that contacts the routing line.

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and an etch mask on the second surface of the metal plate;
• then
• depositing a routing line on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the routing line contacts the first surface of the metal base and the etch mask contacts the second surface of the metal base;
• then
• mechanically attaching a semiconductor chip to the routing line, wherein the chip includes a conductive pad;
• electrically connecting the routing line to the pad;
• forming an encapsulant that contacts and covers the chip and covers the routing line;
• and
• etching the metal base using a first wet chemical etch and then a second wet chemical etch, wherein the first wet chemical etch is selective of the metal plate with respect to the metal layer and the etch mask and etches through the metal plate, thereby exposing the metal layer without exposing the routing line, and the second wet chemical etch is selective of the metal layer and the etch mask and etches through the metal layer, thereby exposing the routing line and removing the etch mask, and an unetched portion of the metal base defined by the etch mask forms a pillar that contacts the routing line.

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and first and second etch masks on the second surface of the metal plate;
• then
• depositing a routing line on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the routing line contacts the first surface of the metal base and the first and second etch masks contact the second surface of the metal base;
• then
• mechanically attaching a semiconductor chip to the routing line, wherein the chip includes a conductive pad;
• electrically connecting the routing line to the pad;
• and
• etching the metal base using a first wet chemical etch and then a second wet chemical etch, wherein the first wet chemical etch is selective of the metal plate with respect to the metal layer and the first and second etch masks and etches through the metal plate, thereby exposing the metal layer without exposing the routing line, the second wet chemical etch is selective of the metal layer and the first and second etch masks and etches through the metal layer, thereby exposing the routing line and removing the first and second etch masks, a first unetched portion of the metal base defined by the first etch mask forms a first pillar that contacts the routing line, and a second unetched portion of the metal base defined by the second etch mask forms a second pillar that contacts the routing line.

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and first and second etch masks on the second surface of the metal plate;
• then
• depositing first and second routing lines on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the first and second routing lines contact the first surface of the metal base and the first and second etch masks contact the second surface of the metal base;
• then
• mechanically attaching a semiconductor chip to the first and second routing lines, wherein the chip includes first and second conductive pads;
• electrically connecting the first routing line to the first pad;
• electrically connecting the second routing line to the second pad;
• and
• etching the metal base using a first wet chemical etch and then a second wet chemical etch, wherein the first wet chemical etch is selective of the metal plate with respect to the metal layer and the first and second etch masks and etches through the metal plate, thereby exposing the metal layer without exposing the first and second routing lines, the second wet chemical etch is selective of the metal layer and the first and second etch masks and etches through the metal layer, thereby exposing the first and second routing lines and removing the first and second etch masks, a first unetched portion of the metal base defined by the first etch mask forms a first pillar that contacts the first routing line, and a second unetched portion of the metal base defined by the second etch mask forms a second pillar that contacts the second routing line.

A method of making a semiconductor chip assembly, comprising:

• providing a metal plate with first and second opposing surfaces;
• then
• depositing a metal layer on the first surface of the metal plate and first and second etch masks on the second surface of the metal plate;
• then
• depositing first and second routing lines on the metal layer, wherein a metal base includes the metal plate, the metal layer and first and second opposing surfaces, the metal layer provides the first surface of the metal base, the metal plate provides the second surface of the metal base, the first and second routing lines contact the first surface of the metal base and the first and second etch masks contact the second surface of the metal base;
• then
• mechanically attaching a first semiconductor chip to the first routing line, wherein the first chip includes a first conductive pad;
• mechanically attaching a second semiconductor chip to the second routing line, wherein the second chip includes a second conductive pad;
• electrically connecting the first routing line to the first pad;
• electrically connecting the second routing line to the second pad;
• and
• etching the metal base using a first wet chemical etch and then a second wet chemical etch, wherein the first wet chemical etch is selective of the metal plate with respect to the metal layer and the first and second etch masks and etches through the metal plate, thereby exposing the metal layer without exposing the first and second routing lines, the second wet chemical etch is selective of the metal layer and the first and second etch masks and etches through the metal layer, thereby exposing the first and second routing lines and removing the first and second etch masks, a first unetched portion of the metal base defined by the first etch mask forms a first pillar that contacts the first routing line, and a second unetched portion of the metal base defined by the second etch mask forms a second pillar that contacts the second routing line.