Thermally enhanced chip scale lead on chip semiconductor package and method of making same

A method of fabricating a semiconductor package, comprising the steps of:

• a) providing a substrate which has first and second lands disposed in spaced relation to each other and a plurality of lead fingers disposed in spaced relation to the first and second lands, the first land defining opposed top and bottom first land surfaces, the second land defining opposed top and bottom second land surfaces, and each of the lead fingers defining opposed top and bottom lead surfaces;
• b) providing a semiconductor chip which has an active surface defining a central region and a peripheral region, and a plurality of connection pads disposed on the central and peripheral regions of the active surface;
• c) attaching the semiconductor chip to the substrate such that at least one of the connection pads is positioned over and electrically connected to the first land, at least one of the connection pads is positioned over and electrically connected to the second land, and at least one of the connection pads is positioned over and electrically connected to at least one of the lead fingers;
• and
• d) at least partially encapsulating the substrate and the semiconductor chip with a package body such that the bottom lead surfaces of the lead fingers are each substantially flush with a bottom surface of the body.

A method of fabricating a semiconductor package, comprising the steps of:

• a) providing a substrate which has a land and a plurality of lead fingers disposed proximate to the land, the land defining opposed top and bottom land surfaces and a plurality of land fingers, and each of the lead fingers defining opposed top and bottom lead surfaces and an outer end;
• b) providing a semiconductor chip which has an active surface and a plurality of connection pads which extend along the active surface in spaced, generally parallel rows;
• c) attaching the semiconductor chip to the substrate such that at least one of the connection pads is positioned over and electrically connected to at least one of the land fingers, and at least one of the connection pads is positioned over and electrically connected to at least one of the lead fingers;
• d) at least partially encapsulating the substrate and the semiconductor chip with a package body such that the bottom lead surfaces of the lead fingers are each substantially flush with a bottom surface of the body.