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US 7,064,007 B2Granted
Method of using foamed insulators in three dimensional multichip structures
AssigneeMicron Technology, Inc.
InventorPaul A. Farrar
Life of this patent
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Abstract
A multichip cube structure having a foamed insulating material disposed between adjacent integrated circuit chips. The foamed insulating material has lower dielectric constant and therefore reduces the capacitive coupling between electrical interconnects on adjacent chips. The foamed insulating material also has higher ductility and lower thermal coefficient of expansion than conventional oxide insulators so as to reduce the occurrence of stress induced cracking in circuitry.
Claims6
A method of manufacturing a multichip cube structure having reduced capacitive loading, comprising:
- forming an insulating layer on an upper bonding surface of a first chip;
- reducing the dielectric constant of the insulating layer by creating a plurality of voids in the insulating layer;
- and
- securing a second chip to the upper bonding surface of the first chip wherein a lower bonding surface of the second chip is positioned adjacent the upper bonding surface of the first chip.
1 more element
Dependencies are inferred from the claim text.