System and method for high frequency, high output swing buffers

An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

• a first pair of transistors and a second pair of transistors that each receives an input differential signal;
• an inductive load that inductively loads said first pair of transistors and said second pair of transistors;
• said inductive load self-biases said first pair of transistors;
• and
• said second pair of transistors generates DC current,
• wherein said inductive load is directly coupled to said first pair of transistors and said second pair of transistors.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• and
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• and
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• and
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said third transistor and said fourth transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• and
• said common mode output of said DC voltage source is coupled to said gate of said third transistor and said gate of said fourth transistor.

A method for increasing output gain of an electronic circuit, the method comprising:

• receiving an input differential signal at a first pair of transistors and a second pair of transistors;
• inductively loading said first pair of transistors and said second pair of transistors;
• self-biasing said first pair of transistors via said inductive loading;
• and
• generating DC current via said second pair of transistors,
• wherein when said first pair of transistors comprises NMOS transistors, then said second pair of transistors are PMOS transistors.

A method for increasing output gain of an electronic circuit, the method comprising:

• receiving an input differential signal at a first pair of transistors and a second pair of transistors;
• inductively loading said first pair of transistors and said second pair of transistors;
• self-biasing said first pair of transistors via said inductive loading;
• and
• generating DC current via said second pair of transistors,
• wherein when said first pair of transistors comprises PMOS transistors, then said second pair of transistors are NMOS transistors.

An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

• a first pair of transistors and a second pair of transistors that each receives an input differential signal;
• an inductive load that inductively loads said first pair of transistors and said second pair of transistors;
• said inductive load self-biases said first pair of transistors;
• and
• said second pair of transistors generates DC current,
• wherein said second pair of transistors are PMOS transistors, when said first pair of transistors comprises NMOS transistors.

An apparatus for increasing output gain of an electronic circuit, the apparatus comprising:

• a first pair of transistors and a second pair of transistors that each receives an input differential signal;
• an inductive load that inductively loads said first pair of transistors and said second pair of transistors;
• said inductive load self-biases said first pair of transistors;
• and
• said second pair of transistors generates DC current,
• wherein said second pair of transistors are NMOS transistors, when said first pair of transistors comprises PMOS transistors.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• and
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein said third transistor and said fourth transistor comprise PMOS transistors, when said first transistor and said second transistor comprise NMOS transistors.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• and
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein said third transistor and said fourth transistor comprise NMOS transistors, when said first transistor and said second transistor comprise PMOS transistors.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• a load inductor coupled to said DC voltage source.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein a first terminal of a first resistor is coupled to said gate of said first transistor.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein a first terminal of a second resistor is coupled to said gate of said second transistor.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein a first terminal of a load inductor is coupled to a drain of said first transistor and a drain of said third transistor.

An apparatus for increasing gain for an electric circuit, the apparatus comprising:

• a first transistor, wherein a gate of said first transistor is coupled to a first differential input;
• a second transistor, wherein a gate of said second transistor is coupled to a second differential input;
• a third transistor, wherein a gate of said third transistor is coupled to said first differential input;
• and
• a fourth transistor, wherein a gate of said fourth transistor is coupled to said second differential input, wherein:
• said first transistor and said second transistor are biased by a common mode output of a direct current (DC) voltage source;
• said DC voltage source is coupled to said third transistor and said fourth transistor;
• said common mode output of said DC voltage source is coupled to said gate of said first transistor and said gate of said second transistor;
• and
• wherein a second terminal of a load inductor is coupled to a drain of said second transistor and a drain of said fourth transistor.