Finite state machine circuit
AssigneeInfineon Technologies AG
InventorsDyson Wilkes, Kostas Spyridis
Life of this patent
Estimating the term…
Abstract
A finite state machine (FSM) circuit including a random access memory (RAM) as the basic logical element and a multiplexer, which can be programmed to perform arbitrary sequences of events. The RAM is used as a state table and output states are fed back to determine the next memory location. The number of locations in the RAM is reduced in comparison with prior art devices, which minimises power consumed by a microprocessor implementing such an FSM. This reduction in the number of locations is possible because only relevant inputs to the RAM are selected. The circuit has both synchronous and asynchronous implementations.
Claims8
A finite state machine, comprising:
- a memory device for providing outputs which depend on inputs to the memory device;
- a device configured to receive input values;
- a multiplexer for selecting a subset of the input values based on an output of the memory device;
- a latch, connected to the output of the memory device, the latch being configured to allow the outputs of the memory device to be read only after a predetermined delay following any change in the inputs to the memory device;
- and
- a control circuit, the control circuit being adapted to trigger a change in the outputs of the memory device following a change in the inputs to the memory device, and to enable the latch after said predetermined delay;
- wherein the outputs of the memory device form the outputs of the finite state machine and a present state of the finite state machine, and
- wherein the present state of the finite state machine and the selected subset of the received input values define the inputs to the memory device.
A signal processing element comprising:
- a finite state machine, including:
- a memory device for providing outputs that depend on inputs to the memory device;
- a device configured to receive input values;
- a multiplexer for selecting a subset of the input values based on an output of the memory device;
- a latch connected to the output of the memory device, the latch being configured to allow the outputs of the memory device to be read only after a predetermined delay following any change in the inputs to the memory device;
- and
- a control circuit, the control circuit being adapted to trigger a change in the outputs of the memory device following a change in the inputs to the memory device, and to enable the latch after said predetermined delay;
- wherein the outputs of the memory device form the outputs of the finite state machine and a present state of the finite state machine, and
- wherein the present state of the finite state machine and the selected subset of the received input values define the inputs to the memory device.
Dependencies are inferred from the claim text.