# US 7,060,512 B2 · Patching methods and apparatus for fabricating memory modules

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- Number: US 7,060,512 B2
- Document ID: US7060512B2
- Status: Granted
- Kind: B2
- Application number: 10/371,663
- Filed: 2003-02-20
- Published: 2003-08-28
- Granted: 2006-06-13
- Earliest claimed: 2002-02-26
- Assignees: Celetronix, Inc.
- Inventors: Charles I. Peddle
- Web page: https://patentgrep.com/patent/US7060512B2

## CPC

- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- G11C 29/022: {in I/O circuitry}
- G11C 29/88: {with partially good memories}
- G11C 29/886: {combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H05K 1/029: {having a programmable lay-out, i.e. adapted for choosing between a few possibilities}
- H05K 1/181: associated with surface mounted components
- H05K 3/225: {Correcting or repairing of printed circuits (H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence)}
- H05K 2201/10159: Memory
- H05K 2203/162: Testing a finished product, e.g. heat cycle testing of solder joints
- H10W 72/581: {Auxiliary members, e.g. flow barriers}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A method and apparatus for building a memory module using improved patching schemes comprises, mounting multiple primary and secondary memory parts on a multi-layer circuit board, positioning I/O bit line patching networks adjacent to the primary and secondary memory parts, matching read/write control signals for primary and secondary memory parts which share I/O bit line patching networks, testing primary and secondary memory parts to identify non-operable I/O lines, and patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part. The method and apparatus include multi-layer circuit boards which utilize 2-to-1, 4-to-1, and 8-to-1 patching configurations.

## Claims

### Claim 1

A method for fabricating a semiconductor memory module on a multi-layer printed circuit board comprising the steps of:
mounting a plurality of primary memory parts on said printed circuit board;
testing said primary memory parts to determine Input/Output (I/O) line functionality;
mounting pre-tested secondary memory parts whose operable I/O lines match failed I/O lines of said primary memory parts;
positioning I/O line patching elements on said printed circuit board adjacent to said primary and secondary memory parts;
matching read/write control signal lines for each respective I/O line of one of said primary memory parts with a like I/O line of an individually associated secondary memory part;
patching any non-operable I/O line of a primary memory part by replacing it with a fully-operable I/O line of its associated backup memory part by selectively connecting and disconnecting patching elements corresponding to a functional I/O line of said secondary memory part and a non-functional I/O line of said primary memory part.

### Claim 2 (depends on 1)

The method of claim 1, wherein said step of positioning comprises a step of forming on said PC board a multi-column essentially a two-dimensional ladder-like structure of isolated conductive pads for facilitating connection of working I/O line segments of said matched read/write control lines to enable a working I/O line of its associated backup memory part to replace a non-working I/O line of one of said primary memory parts.

### Claim 3 (depends on 1)

The method of claim 1, wherein the step of patching comprises the step of selectively establishing an electrical connection between selected ones of the conductive pads of two of said isolated columns and electrically isolating said selective ones of said conductive pads from other conductive pads in a same column.

### Claim 4 (depends on 3)

A semiconductor memory module fabricated in accordance with claim 3.

### Claim 5 (depends on 1)

A semiconductor memory module fabricated in accordance with the method of claim 1 wherein said primary and secondary memory parts comprise at least one less than fully operational memory parts.

### Claim 6 (depends on 1)

The method of claim 1, wherein 4 and 8M×64 SDRAM DIMM said bit patching network comprises a total of 32 patching network elements for simultaneously accessing a 64 bit word.

### Claim 7 (depends on 1)

The method of claim 1, wherein the patching network comprises a 4-to-1 patching network configuration.

### Claim 8 (depends on 1)

The method of claim 1, wherein said patching network comprises a 2-to-1 patching network configuration.

### Claim 9

A method for fabricating a semiconductor memory module on a multi-layer printed circuit board comprising the steps of:
mounting a plurality of primary memory parts and secondary backup memory parts on said circuit board,
positioning a lattice type I/O line bit patching network adjacent ones of said primary and said secondary memory parts,
matching read/write control signal lines for each respective I/O line of one of said primary memory parts with a like I/O line of an individually associated secondary memory part,
testing each primary and secondary memory part to identify any non-operable I/O lines, and
patching any non-operable I/O line of a primary memory part by replacing it with a fully operable I/O line of its associated backup memory part by selectively coupling one of said matched read/write control signal lines to said adjacent bit patching network to form a fully operational memory module.

### Claim 10 (depends on 9)

The method of claim 9, wherein said step of positioning comprises a step of forming on said PC board a multi-column essentially a two-dimensional ladder-like structure of isolated conductive pads for facilitating connection of working I/O line segments of said matched read/write control lines to enable a working I/O line of its associated backup memory part to replace a non-working I/O line of one of said primary memory parts.

### Claim 11 (depends on 9)

The method of claim 9, wherein the step of patching comprises the step of selectively establishing an electrical connection between selected ones of the conductive pads of two of said isolated columns and electrically isolating said selective ones of said conductive pads from other conductive pads in a same column.

### Claim 12 (depends on 11)

A semiconductor memory module fabricated in accordance with claim 11.

### Claim 13 (depends on 9)

A semiconductor memory module fabricated in accordance with the method of claim 9, wherein said primary and secondary memory parts comprise at least one less than fully operational memory parts.

### Claim 14 (depends on 9)

The method of claim 9, wherein said patching network comprises an 8-to-1 patching network configuration.

### Claim 15

A semiconductor memory module including a plurality of primary memory parts and a plurality of secondary backup memory parts, at least one of said secondary backup memory parts having one or more defective I/O output line segments, said memory module comprising:
a multi-layer PC board for supporting said primary and secondary memory parts on at least one outer surface thereof,
a plurality of I/O bit patching networks at least one of which networks is positioned adjacent each memory part,
a first conductive pathway on said PC board for combining individual memory parts read/write control lines of each primary memory part with an associated backup memory part,
a second conductive pathway on said PC board for connecting each said individual combined read/write control line to a predetermined conductive tab of a first of said bit patching networks adjacent to a pair of predetermined associated primary memory part and its associated backup secondary memory part, and
a third conductive pathway for selectively establishing an electrical connection between said first and said second conductive pathways with said bit patching network to operatively replace a non-operable I/O line of a primary memory part with an operable I/O line of said associated backup secondary memory part.

### Claim 16 (depends on 15)

The semiconductor memory module of claim 15, wherein said third conductive pathway comprises a solder dot connection.

### Claim 17 (depends on 15)

The semiconductor memory module of claim 15, wherein said third conductive pathway comprises a wire jumper.

### Claim 18 (depends on 15)

The semiconductor memory module of claim 15, wherein said first and said second conductive pathways comprise conductive leads formed on one surface of said PC board.

### Claim 19 (depends on 15)

The semiconductor memory module of claim 15, wherein said plurality of bit patching networks comprise a plurality of individual ladder-like structures of conductive tabs arranged in a plurality of parallel columns and a plurality of conductive tabs arranged in a like parallel column intermediate said ladder-like structure.

### Claim 20 (depends on 15)

The semiconductor memory module of claim 15, wherein said I/O bit patching network comprises a first columnar array of a plurality of individual conductive pads for connecting said I/O segments of a primary memory part, second and third columnar arrays of conductive paths parallel to and on either side of said first columnar array, said second and third array of conductive paths electrically connected to predetermined I/O segments of said primary memory module, and a plurality of conductive jumpers for connecting a pre-selected tab of said first array to predetermined ones of said conductive tabs of said second or third array of conductive paths to selectively connect one or more of said fully operable I/O data lines as outputs for said memory module.