Data processor memory circuit

A method of predicting which region of a memory circuit will next be accessed during execution of program code by a processor, said memory circuit having a plurality of memory cell arrays each memory cell array having a respective plurality of memory cells that are collectively settable to said readable state or said unreadable state, said method comprising:

• identifying a transition instruction in said program code, said transition instruction being associated with a transition between said processor accessing a currently active memory region and said processor accessing a next target memory region of said memory circuit;
• storing a transition address, said transition address corresponding to said transition instruction;
• storing in relation to said transition address a respective region identifier that identifies said next target memory region;
• checking said stored transition address on each processor access to said memory circuit to determine if a current program instruction corresponds to said transition address;
• initiating a transition of said subsequently active memory region from said unreadable state to said readable state in dependence upon a result of said checking of said stored transmission address.

Memory access prediction circuitry operable to predict which region of a memory circuit will next be accessed during execution of program code by a processor, said memory circuit having a plurality of memory cell arrays each memory cell array having a respective plurality of memory cells that are collectively settable to said readable state or said unreadable state, said memory access prediction circuitry comprising:

• identifying logic operable to identify a transition instruction in said program code, said transition instruction being associated with a transition between said processor accessing a currently active memory region and said processor accessing a next target memory region of said memory circuit;
• storage means operable to storing a transition address, said transition address corresponding to said transition instruction and to store in relation to said transition address a respective region identifier that identifies said next target memory region;
• comparator logic operable to check said stored transition address on each processor access to said memory circuit to determine if a current program instruction corresponds to said transition address;
• wake-up logic operable to initiate a transition of said next target memory region from said unreadable state to said readable state in dependence upon a result of said check of said stored transmission address.