Level shifter utilizing input controlled zero threshold blocking transistors
AssigneeSamsung Electronics Co., Ltd.
InventorJin-Ho Seo
Life of this patent
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Abstract
Level shifter circuits include zero threshold transistors that reduce a voltage seen by a switching transistor of the level shifter circuits and may increase blocking of static current in the level shifter circuit. The zero threshold transistors are controlled based on the input to the level shifter circuit. Thin oxide transistors may be used to provide low threshold voltages for the switching transistors. Additional level shifter circuits include serially connected zero threshold transistors that act as switching transistors in a current mirror or latch-type level shifter circuit.
Claims23
A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
- a current mirror circuit that provides an output signal in the second power domain, the current mirror comprising:
- first and second p-type transistors coupled to the second supply voltage;
- first and second zero threshold n-type transistors coupled to respective ones of the first and second p-type transistors;
- and
- first and second n-type transistors coupled to respective ones of the first and second p-type transistors through respective ones of the first and second zero threshold transistors, the first and second n-type transistors having a threshold voltage based on the first supply voltage;
- and
- a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.
A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
- a current mirror circuit that provides an output signal in the second power domain, the current mirror comprising:
- first and second p-type transistors coupled to the second supply voltage;
- first and second zero threshold n-type transistors coupled to respective ones of the first and second p-type transistors;
- and
- first and second n-type transistors coupled to respective ones of the first and second p-type transistors through respective ones of the first and second zero threshold transistors, the first and second n-type transistors having a threshold voltage based on the first supply voltage;
- a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal, wherein the switching control circuit comprises a delay circuit configured to delay the input signal to provide a delayed input signal to control the first zero threshold transistor;
- a first inverter utilizing the first supply voltage and configured to receive the input signal and provide an inverted input signal to the first n-type transistor;
- a second inverter utilizing the first supply voltage and configured to receive the inverted input signal and provide a buffered input signal to the second n-type transistor;
- and
- a third inverter utilizing the second supply voltage and to provide the output signal.
A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
- first and second cross-coupled p-type transistors coupled to the second supply voltage;
- first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal;
- and
- third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal.
A level shifter for shifting an input signal from a first power domain having a first supply voltage to a second power domain having a second supply voltage, comprising:
- first and second p-type transistors coupled to the second supply voltage having connected gate electrodes;
- first and second zero threshold n-type transistors serially coupled to the first p-type transistor and responsive to an inverted input signal;
- third and fourth zero threshold n-type transistors serially coupled to the second p-type transistor and responsive to an buffered input signal;
- and
- a switching control circuit utilizing the first supply voltage that controls the first zero threshold transistor responsive to the input signal.
Dependencies are inferred from the claim text.